The increasing amount of data that has to be processed in today’s electronic devices requires a transition from the conventional compute centric paradigm to a more data centric paradigm. In order to bridge the existing gap between memory and logic units that is known as the classical von Neumann bottleneck the concept of physical separation between computing and memory unit has to be repealed. Neuro inspired architectures constitute a promising solution where both logic and memory functionality become synergized together in one synaptic unit. Our project BeFerroSynaptic addresses the specific challenges of the H2020-WP 2018-2020 by targeting for the development of electronic synaptic devices based on one of the most power-efficient memory technologies – the ferroelectric polarization switching. The ultimate goal of the BeFerroSynaptic project is to develop a ‘ferrosynaptic’ technology platform featuring back-end-of-line (BEOL) integrated Hf(Zr)O2-based ferroelectric field-effect transistors (FeFETs) and ferroelectric tunnelling junctions (FTJs) on top of an existing CMOS technology. Our attempt is to demonstrate the feasibility (TRL 4) of the ‘ferrosynaptic’ concept in an extremely energy-efficient neuromorphic computing architecture. To ensure a realistic endeavour, the ambitious challenges will be tackled by building the complementary FTJ and FeFET device development on existing technologies and adapt it to BEOL integration on top of a CMOS technology, and building on existing neuromorphic processor designs that will be adapted to the ‘ferrosynaptic’ technology. The BeFerroSynaptic consortium assembles a significant amount of resources and expertise. It includes representatives both from the academic and research community as well as from industry. The consortium is composed of 11 partners, of which 5 RTOs partners (CEA, NaMLab, NCSRD, IUNET, HZB), 4 universities (UZH, ETH, UG, TUD as project consultant) and 2 industrial partners (X-FAB, IBM).