The past several decades have been marked by the exponential growth of computer-generated data and related information processing. Such growth continues now, e.g. with the deployment of gigabit internet and 4G wireless networks, and will likely be accelerated by emerging technologies such as robotics, biotechnology, and distributed sensor networks. Given the inevitable end of scaling of conventional semiconductor circuits and increasing energy-use awareness, alternative ways to allow for information processing in an energy efficient fashion must be developed: Nanotechnologies open the way to new computing paradigms and circuits that could replace the actual technology based on Von Neumann architecture and CMOS devices. The aim of this project is to develop hardware systems of memristive nanodevices for neuro-inspired computing. Different promising ideas have been proposed for alternative computing solutions based on bio-inspired computing paradigm, such as perceptron, associative memory or Bayesian inference. These propositions are particularly promising for classification, recognition or anticipation tasks, which are hardly implement in conventional computers. If theoretical works are already available for estimation of performances and functionalities demonstration, experimental realization of these computing systems represent a challenge with high impact potentiality. The recent proposition of memristance by D. Strukov based on RRAM technology offers a unique opportunity to bridge the gap between theory and experiment by providing simple two terminal nanodevices that could match the requirement in terms of memory density and parallel interconnect for such circuits. I propose in this project an approach based on the development in parallel of (i) a specific technology for neuro-inspired computing - more precisely, the successful technology will implement the synaptic operation by coupling analog memory (or multistate resistance) and plasticity properties (i.e. tuning of memory volatility) – and (ii) the realization of hybrid circuits for neuro-inspired function demonstration and evaluation. These hybrid circuits will be built with hardware integrated nanodevices and Integrated Circuit breadboarding. This approach is directly compatible with hybrid CMOS/nanodevices circuit development that is envisioned for such neuro-inspired systems. If successful, such approach would allow orders of magnitude energy savings in information processing and enable more functional electronics.