As the fabrication dimensions of devices have reduced, the variability of their electrical parameters has increased. This effect can lead to circuit failure, particularly for low-power circuits designed in very small geometry processes. This problem may result in the potential of processes with 45 nm, 22 nm Leff and below not being fully realised. Current cell designs, such as those for SRAM cells have failure rates for the random fluctuations envisaged at 22nm that make large SRAM arrays unviable, and other cells have timing variations which force the clock rate to be unacceptably slow. This three-year proposal aims to develop techniques to develop robust cell circuits, and to develop design tools and techniques for circuits which will deliver the reliability and performance necessary in cell libraries for future multi-billion-transistor SoC.The main goals of the project are: (1) Evaluate circuit design tools for cell design in the face of severe and random process fluctuations, (2) Show how these tools can be improved to assist circuit designers achieve higher productivity, (3) Design more robust integrated circuits capable of good performance in nanometre technologies, with low supply voltages and large parameter fluctuations, (4) Derive general principles for robust cell design in nanometre processes, and to evaluate them in a realistic demonstrator