We are at a pivotal point in the design of computational devices.Technology scaling favours transistors over wires which has moved usinto an era where communication takes more time and consumes morepower than the computation itself. We believe that this technologydriver inextricably pushes us toward a communication-centric approachto computer system design from both hardware and softwareperspectives. This grant application is focused on exploring this newcommunication-centric view of computer system design from engineeringwires through computer architecture, compiler design, language designand application mapping. It is our wish that this grant form aportfolio of projects tackling future computational systems involvingthousands of power efficient processors.Communication-centric design can be viewed at several levels ofabstraction:Level 0 - implementation technology, where we will focus oncommunication networks-on-chip.Level 1 - computer architecture, focusing on optimisation ofcommunication flows in the system.Level 2 - algorithm mapping to allow automated placement of data andcode across a manycore computing surface.Level 3 - programming language and compiler design to allowparallelism and locality to be easily expressed.An FPGA based simulation infrastructure will also be constructed toallow research results to be obtained from hardware work at levels 0and 1, and to efficiently support software research undertaken atlevels 2 and 3.