This proposal is concerned with the automatic design of reconfigurable architectures. The proposed approach forms a radical departure from standard industrial and academic practice in reconfigurable architecture design. The main feature of this approach is its basis in formal global optimization proceduresfrom the mathematical programming and operations research communities, in contrast to the empirical approaches typically used to attack this problem.The intention is to develop and extend mathematical models of power consumption, computation throughput, and silicon area usage, and incorporate these within a mathematical programming framework. This will allow the simultaneous optimization of multiple architectural and synthesis parameters, leading to provable-quality solutions, and eliminating the dependence of the resulting architecture on heuristic bias.Promising preliminary results have already been achieved, providing provably optimal bounds on the relative computational speed of various DSP benchmarks compared to ASIC implementations of the same circuits, and proposing architectures resulting in up to 20% speed improvement (for the same area) or 60% area reduction (for the same speed) over commercial architectures.Funding is requested for a post-doctoral research associate (3 years) and a Ph.D. student (3.5 years) to work with the investigators.