The objective of the 10Ce pThe objective of the 10Ce project is to explore and realize solutions for the 10 CMOS chip technology. Its consortium covers the entire value chain for manufacturing of the CMOS chips in the 10A node, that is, from chip design to lithography to process technology and finally chip metrology. Essential parts of hardware, software and processing technology are developed pushing the boundaries of semiconductor design and manufacture to enable the new node and keep Moores law alive. The 10Ce project is built based on the following four pillars. Lithography Equipment: ASML and expert EUV partners Zeiss, FastMicro, IOM, Plasma Matters, TNO, TU/e, University of Twente and VDL-ETG will: Increase key performance indicators of the EUV tool, to enable smaller pitches and increase yield. Increase sustainability of the EUV tool, both during production as well as increasing the times a module in an EUV tool can be refurbished. Chip design and mask optimization: Imec with the involvement of expert imaging , CAD and IP design partners ARM, ASML and Siemens will: Assess the impact of the introduction of 3D mCFET on chip design: in terms of power, performance and area. Development of new computational lithography solutions to print 10 CFET structures, to improve imaging by next generation mask design. Process Technology: As the ultimate device for logic, the CFET architecture is proposed and Imec and expert partners Coventor, EVG, IBS, Intel, JSR, LAM, RECIF, TEL, Zeiss and Wooptix will: Demonstrate a fully functional monolithic CFET (mCFET) Increase sustainability of the chip manufacturing process, across the manufacturing process and including resist material development. Process characterization: Applied Materials and expert partners Thermofisher, Nova, KLA and Bruker will: Explore and realize high throughput and sample density per wafer, for the analysis, characterization for 10 3D CFET devices, interconnect and materials