Solid state electronic devices have transformed our lives over the past fifty years: the development of devices like the transistor, integrated circuits and magnetic hard disks have given us a revolution in computing power, portable electronics and the ability to store and handle vast amounts of data. Quantum technologies aim to harness the power of quantum physics to deliver a further revolution in areas such as computing, sensing and communication. The UK is currently making a major investment in the exploitation of quantum science research to deliver a range of quantum technologies - so far this investment has focused on platforms of photonics, cold atoms and trapped ions. The aim of our proposal, Quantum Engineering of Solid-State Technologies, or QUES2T, is to address the capability gap in in quantum solid-state technologies and ensure the UK is in a strong competitive position in some of the most high-impact and scalable quantum technologies. In QUES2T we focus on three solid-state platforms which are well-poised to make significant commercial impact: i) silicon nano-devices, ii) superconducting circuits and iii) diamond-based devices. Each of these materials have demonstrated outstanding properties: silicon can store quantum information for a record-breaking 3 hours, superconducting circuits have been used to make the most complex quantum devices to date, while diamond based magnetometer have a sensitivity to image individual proton spins in a second. We will exploit these properties to develop practical quantum technologies. Importantly, we do not consider these platforms in isolation. A key strength and unique feature of QUES2T is that it not only provides essential infrastructure in each of these three areas but that it brings together a team of people with expertise across these different platforms. This will allow exchange of cross-fertilisation of different disciplines through transfer of expertise and the accelerated development of hybrid technologies that combine the best properties of different materials, to make new detectors, memories, and processors. QUES2T will allow UK researchers and their collaborators to exploit the advantages of developing new quantum devices based on solid state technologies, including easier integration with existing conventional technologies (such as CMOS processors) and reduced timescales to market and manufacturing. The capital infrastructure of QUES2T will establish world-class fabrication capabilities to manufacture high-quality quantum device prototypes out of a range of materials. It will also enable the creation of low-temperature technology test-beds to test the prototypes and develop technology demonstrators. These test-beds will combine a number of essential features, enabling devices to be addressed optically using lasers, with microwave pulses, under low-noise electrical measurements, and all at a hundredth of a degree kelvin. Such systems will be unique UK. To deliver our vision, we have established strong links with academic and industrial partners to exchange the latest technology, expertise and materials. Examples are ultra low-phase noise signal generators with applications in fast high-fidelity qubit control or isotopically pure materials for quantum prototypes in Si and diamond. Industry users working on quantum technologies will be actively encouraged to access the QUES2T infrastructure, such as a state-of-the-art 100 keV electron beam writer to make devices with 10nm features. Many industry partners will also be end users of the technologies that will be developed through QUES2T. Early technologies include scanning probe devices enabling magnetic resonance imaging at the single molecule level and quantum current standards counting electrons one-by-one. On a longer timescale, a fault-tolerant and scalable Si or superconducting based quantum processor, would be form the basis of a new and disruptive industry in computing.

For future ICT industry, the elephant in the room is Internet of Things (IoT) and Artificial Intelligence (AI). They are driving the fourth industrial revolution that is profoundly changing how we live and interact. The main issues for IoT and AI have been identified as: power, security, and cost. This project is co-created with the industrial partners and focuses on the power issue. One of the most effective way for reducing power is by lowering the operation voltage, Vg, towards the transistor threshold voltage, Vth. This has motivated recently extensive research in near threshold voltage computing. As Vg approaches Vth, the operation window (Vg-Vth) reduces and the system will be increasingly vulnerable to instability in Vth: a small rise in Vth can effectively switch off a transistor. Instability causes faults in operation, such as read and write errors in SRAM and digital timing errors. It is a limiting factor for how low (Vg-Vth) and, in turn, how much power consumption can be reduced. One of the critical tasks for low power system optimization is to minimise operation voltage and power consumption that will deliver specified yield 'Y' in 'X' years at a temperature below 'T'. To complete this optimization, designers need a fault analysis model that gives the time evolution of the probability distribution of Vth and driving current, Id, at a given distance from their target values. The further Vth and Id depart from their target values, the more likely a circuit will fail. Despite of decades of research, a reliable fault model is still not available. Indeed, in a recent review, the lack of realistic fault model tops the list of challenges for Cognitive Computing System design. Although the need for this model is clear, even world-leading EDA suppliers and foundries cannot deliver the model and current SPICE models simply do not include Jitter. This is related to weaknesses of previous research, including statistically inconsistent bottom-up methodology, limited time window, weak model verification criterion, and the neglect of the interaction of different instability sources. The fabless UK IC-design companies are using foundries for their chip fabrication. Software is the essential bridge between designers and foundries. As there are no generally accepted realistic fault models at present, designers have to rely on adding a guard-band (design margins) obtained from empirical 'worst case guess'. This contributes to the substantial discrepancy between design and Si performance. As CMOS nodes are downscaled to nano-meter range, the stochastic spreading of device parameters increases dramatically this discrepancy, which has been identified as a major challenge for optimizing the design of low power IoT and Cognitive Computing Systems. The aim of this project is to provide the world first test-proven fault model that enables statistical, dynamic, and quantitative analysis of fault rate and in turn the optimization of low power IoT and Cognitive Computing Systems. Novel techniques and methodologies will be employed to overcome the weakness of early works, including a top-down approach to remove device selection, advanced data acquisition method for long time window, qualifying the model by prediction capability, covering the interactions between different sources of instabilities. The developed model will be tested against Si performance of real circuits together with the industrial project partners. If successful, it will deliver a paradigm shift from one-size-fit-all to application specific fault analysis and optimization, reducing power and time-to-market.

Thin oxide films are critical components in a very wide range of electronic devices, including CMOS transistors in microprocessors and memory, piezoelectric and thermoelectric devices and electroluminescent devices. In most cases we assume that the oxide itself is stable under the levels of electrical stress encountered during normal device operation, and a great deal of work has gone into growing extremely high quality films. Nevertheless, recent developments in devices and materials have led to the growing use of amorphous and polycrystalline sub-stoichiometric oxide thin films (SSOTFs). These materials are fundamentally different to their stoichiometric and crystalline cousins - a fact that can have very important consequences for their use in electronic devices - but it is usually assumed that they behave in the same way. It is increasingly clear that this assumption is incorrect. Recent studies, some performed by us, have demonstrated that amorphous sub-stoichiometric oxides are surprisingly dynamic under device-level electrical stress. In the case of silicon oxide, for example, we have shown that electrical stress drives the segregation of the oxide into regions with varying oxygen deficiency, and that such changes can be precursors to major changes in the electrical properties of the material. Our initial results suggest that oxide microstructure determines the ease with which oxygen can segregate, and we have seen, in extreme cases, emission of oxygen from the thin films. These changes can be permanent or they can be reversible, enabling cycling between two or more resistance states. Ultimately, such large-scale changes can lead to device failure. Consequently, by understanding how to control their dynamics we can both understand the early stages of oxide failure, and develop exciting new technologies that exploit the dynamic nature of functional oxides. In this study we propose to investigate these changes using a combination of high resolution experimental characterisation and atomistic modelling of oxygen movement. Studying sub-stoichiometric amorphous oxide thin films is a considerable challenge, both for experiment and for modelling, which is partly why these materials are poorly understood. We will rely on close interaction between experiment and theory to develop, in an iterative process, new models for the structure of substoichiometric amorphous oxides of varying morphology, and their dynamic response to electrical stress. These models will shed light on the physical processes governing electrical changes, and we will use them to generate a set of design rules for material and device optimisation. We have chosen a representative set of materials to study, each of which has important applications in microelectronics. We will grow the materials in-house, giving us control over their composition and structure and enabling rapid feedback from characterisation and modelling. The majority of our characterisation will also be performed at UCL, but we have long-standing and fruitful collaborations with two leading Transmission Electron Microscopy centres - Forschungszentrum Jülich and the Institute of Materials Research and Engineering in Singapore - which will give us access additional world-leading microscopy techniques to study these challenging materials. Our close collaboration with other leading research and development institutions, including our industrial partners, gives us access to further state-of-the-art facilities and industrially relevant samples.

Following the Moore's law the semiconductor industry has delivered continuous increase of systems functionality and speed over the last 50 years through the aggressive downscaling of the transistors. In the last 20 years the UK IC-design based industry has grown to a level of national and international importance. While IC designers in the past enjoyed the freedom that all transistors in a chip could be treated identically, this is no longer the case for the nano-meter sized transistors used in the present and future technologies. Statistical device-to-device variation is introduced by the discreteness of charge and granularity of matter and is inversely proportional to gate area, so that its impact on circuits increases with the reduction of transistor dimensions. When the number of logic gates in a system increases and the architecture becomes more complex, the tolerance to variability is greatly reduced. Even if two devices were identical after fabrication, they could suffer from different aging during operation, causing a time-dependent variability (TDV). TDV is becoming a major threat to the correctness of electronic systems, but there are no tools for its verification because of the lack of a complete understanding. The aim of this project is to carry out an in-depth investigation of the defects and mechanisms responsible for TDV and, based on that, to develop a test-proven TDV simulator, allowing IC designers to assess the impact of TDV on their circuits. The researchers at Glasgow University have pioneered variability simulation and the researchers at Liverpool John Moores University have specialised in experimental characterization of defects. Their highly complementary skills bring them together and make them well positioned to tackle this challenge. By working together with UK companies, the impact of their work on UK industry will be direct. The collaboration with IMEC and its industrial consortium also opens an effective impact pathway on an international scale. The successful control of TDV will deliver reliable electronic products and minimize their power consumption.

The semiconductor industry has provided the devices we have enjoyed for many years, including mobile phones, personal computers, on-line banking etc. The growing functionality of these products is a result of making the components, namely transistors and memory elements, ever smaller, at the rate that in every 18 months or so the number of components in a given area has doubled, which also makes the devices run faster. The industry now runs into a fundamental roadblock in shrinking the devices further, so we need to look for a new device type which will continue to provide higher performance. One strong contender is the RRAM (resistive random access memory) which we will investigate in this project. This device can be programmed to offer either a high or low electrical resistance: that is, store a logic "0" or "1", or even with some intermediate levels in between. It can store information which will remain even after the power is turned off, as so called non-volatile. With this device, a number of disruptive developments are under intensive research world-wide. Its first potential application is to increase the speed of the non-volatile memory chip in computers by more than 10 times and provide potential for further increase in the number of components. The second is in the artificial intelligence (AI) computing which mimics the functionality of human brains. AI has been widely used by Google, Facebook, Apple, etc. RRAM has the potential to bring a breakthrough in AI by solving the density, connectivity and memory bandwidth limitations of AI hardware based on conventional devices. The third is to revolutionise the programmable computing with its smaller size and non-volatility, providing advantages for computing in data centres and Internet of Things, in which the vast amount of data will be streamed through internet and the scalability and energy efficiency provided by RRAM become critical. The behaviour of RRAM devices, however, is stochastic, meaning that a large variation occurs during the device operation. At present, the lack of systematic understanding of the variability and the missing tools for variability-aware simulation hinder the research progress in RRAM-based circuit and systems design for neuromorphic and programmable computing. In this project we will collaborate with UK's leading IC design company, ARM Holdings, and the world no.1 EDA software company, Synopsys, providing direct insight into the fundamental properties of RRAM variability and developing a predictive variability-aware product design kit (PDK) that can be directly used within commercial EDA software by designers, enabling the research and design of novel RRAM based neuromorphic and programmable computing systems. We expect this project to have a significant direct impact on the UK and global ICT industry in the forthcoming Artificial Intelligence (AI) and Internet of Things (IoT) era.