This project investigates a promising solid state architecture that could be extended to build a quantum information processor. We focus on a well understood system, the NV-defect centre in diamond. This centre has a ground state spin that is well coupled to photons such that arrays of spins coupled by low loss waveguides can be envisaged. However the solid state brings increased decoherence and spectral non-uniformity compared to atomic systems. It also brings the prospect of building spin and photonic interfaces at scale, using nanofabrication. Here we aim to individually address solid-state emitters control their spin and make them spectrally indistinguishable thus ensuring high fidelity spin quantum bits linked by waveguides on a chip. While most of the focus of the solid-state quantum photonics community has been devoted to finding an ideal solid-state emitter that exhibits atom-like properties, relatively little effort has been spent on figuring out how one can build complex opto-electronic systems around them enabling precise optical and spin control. This is especially important, given that traditional top-down semiconductor manufacturing methods cannot be directly applied to such bottom-up systems. Since a fully error corrected quantum computer will need O(1E6) qubits and even near-term noisy intermediate scale quantum (NISQ) devices need O(1E2) to demonstrate computational quantum supremacy, there is an urgent need to establish that bottom up systems employing solid state emitters can be scaled up to be competitive with top-down fabricated systems (such as those employed for linear optics and superconducting circuits). The NV- centre provides a room-temperature quantum system with optical and spin degrees of freedom that can be accessed and manipulated and this room temperature readout makes the NV- centre attractive for rapid iteration and prototyping of devices, both in the electrical and optical domain. In addition, the ready availability of high coherence NV- centres in nanodiamond form allows us to directly implement bottom-up manufacturing methods, originally developed in the bio-chemistry domain, such as precision localisation and templated self-assembly to solid state quantum optics.

Computing pervades our lives, impacting our health, work, entertainment and social interaction. Over recent years, the technology inside the devices providing these services has undergone a radical change: where once, processing was undertaken by relatively homogeneous "sequential" devices, in which essentially one thing happened at a time, the new systems compose a range of specialized devices, some targeting specific problem sub domains, and almost all exhibiting considerable "parallelism", where many things can happen at the same time. This is true on all scales, from the internals of a mobile phone, to the massive data centres which serve web applications such as Google. This poses a substantial challenge for the software industry: writing correct and efficient programs for heterogeneous, highly parallel systems is much harder than for current technologies and most developers lack the skills and training to write safe and efficient code. Faced with this difficulty, software developers will often avoid writing parallel code completely, or else will use inappropriate, non-scalable and error-prone approaches based on explicit threads of program execution. Given the hardware trend towards increasingly complex, increasing parallel (manycore) systems, this is an inherently short-term strategy that is doomed to failure, Our project addresses this issue. Our key insight is that humans in general, are very good at using patterns to understand, predict and act in the real world. This insight translates into the world of software engineering in general, and parallel heterogeneous programming in particular. Our work will help programmers to recognize patterns in pre-existing and new applications, and to transform these pattern occurrences into forms which allow them to be exploited, adapted and run effectively on the new hardware platforms. The systems we develop will work in partnership with software developers, reducing the complexity of the task, automating and semi-automating the development task. The result will help the industry to develop new applications, and to update existing applications, with less effort, fewer errors and better resilience as the underlying technology continues to evolve.

There is insufficient radio spectrum below 6GHz to cater for future mobile communications demand. Researchers are also now beginning to consider the needs of the 2030 intelligent information society, which will likely include a further push into sub-terahertz radio spectrum, to deliver yet more user data bandwidth. In 5G, future 6G and beyond, use of millimetre wavelength (mmWave) bands in fixed wireless access and handheld equipment will require power efficient, low cost yet high-performance RF transceivers. Such transceivers must also support extremely high data rates (e.g. Gigabit Ethernet; 5Gbit/s for USB 3.0; 10's of Gbit/s peak rates for vehicular 'infotainment' and '8k' ultra-high-definition TV for virtual reality). This challenging set of requirements has, to date, been mutually exclusive in all conventional mmWave technologies. With the release of early 5G smartphones, such as Samsung Galaxy S10 5G incorporating 28GHz / 39GHz communication radios (bands n257-n261), the era of mmWave mobile communications has begun. Although entry-level 5G is in early stage deployment (using modifications to 4G), it is unlikely to be defined or viable for deploying at high mmWave bands (circa 73GHz) before 2030. Initial analysis shows the digital signal processing (DSP) required for multi-Gbit/s data may extend to 10's of billions of 'multiply-accumulate' instructions per second. When combined with analogue radio functions, this could result in consumed battery powers of 14W by receive functions alone, with considerably more for transmit. Smartphone battery capacities are now circa 4.5Ahr, which would support just 1 hour of operation at such consumed receive powers. Thus, there is an urgent need for new research into mmWave radio hardware and software architectures, for frequencies at E band (circa 73GHz) and beyond. The Fellowship will focus on the following areas:- 1) Cost-effective and power-efficient techniques to form mmWave antenna arrays. Our recent research into Time Modulated Antenna Arrays (TMA) has shown ways of improving TMA efficiency at lower frequencies. A key attraction of the TMA is its simplicity of control interface (all digital). 2) Reinvestigation of fundamental mmWave circuit concepts, such as mixers and oscillators, using new insight and making use of the latest findings for manufacturing key components such as resonators. The research in resonators at mmWave could now benefit from the latest 3D printing techniques available at the University of Sheffield as well as updated techniques in low temperature co-fired ceramics. 3) A holistic view of the mmWave transceiver in terms of hardware and software, with partitioning to give best power efficiency for an RF performance target. Novel techniques will be valuable in saving power in massive multiple-input multiple-output systems (M-MIMO), having many hundreds of antennas and transceivers. In existing M-MIMO systems the power consumed by RF hardware could rival that of the digital signal processors. Research will include reconsidering long-forgotten circuit topologies and ideas, in this new setting. 4) Exploration of signal processing techniques for mmWave cognitive radio- allowing it to sense its operational environment and optimise its performance (via reconfigurable RF hardware). Also, the emergence and increase in capability of artificial intelligence is now becoming relevant for operation closer to the hardware itself, such as in demodulating an incoming RF signal. 5) Prototype test chips and subsystems will be created during the project. These will be used to build mmWave radio system demonstrators, including for propagation measurement research. The post-fellowship application for the trial platforms will support further research in future mass-producible mmWave systems, as well as facilitating enhanced industry engagement.

The internet transmits data with a rate of hundreds of Terabits per second (Tbit/s), consumes 9% of the worldwide produced electrical energy and is growing at a rate of 20 - 30 % per year. One single carrier produced by a laser diode, can provide the data transmission of 26 Tbit/s. By combining optical carriers with TeraHertz (THz) waves as well, data rates of several Tbit/s can be transmitted over a wireless link, which will enable hybrid optical/THz wireless links. The next/sixth generation (6G) communication network is expected to be commercialised from 2030. 6G will generate greater diffusion and provide technical platforms to solve social, economic and humanity issues with higher data rates, wider bandwidth and lower latency. The urgency and challenges require the development of revolutionary technologies to meet the projected performance levels. These developments are captured in the recent beyond-5G roadmaps from research forums such as WWRF, NetWorld2020, H2020 5G-PPP, 6G-Summit, USA NSF, industry organizations including 3GPP, IEEE, ETSI, ITU-R, ITU-T, and spectrum regulatory forums e.g., FCC, ECC, OFCOM, WRC'19 [https://doi.org/10.3390/electronics9020351]. At the University of Glasgow (UofG), more than 10 research groups in James Watt School of Engineering are working on enabling technologies in the area of wireless communications, optical networking and a mix of fibre optics, millimetre wave and ultrafast THz wireless links. Such concepts require novel semiconductor devices and circuits that must be characterised at an early stage of development, i.e. at chip level, once they are manufactured at our James Watt Nanofabrication Centre (JWNC). To support this research, this project aims to establish an on-chip device and integrated circuit test cluster together with a carrier independent, ultra-high data transmission rate and processing system to measure key performance indicators in both the user and control planes. The proposed Test Cluster is the first of this kind in the world that allows complex signal and waveforms directly deployed to devices under test on chip. This will trigger new device concepts as well as enable development of transceiver architectures. This work will potentially create industry game changers. The Cluster consists of three key modules: waveform generation, signal analysis, and device characterisation. The three modules can operate individually or collectively and are built around a semi-automated probe station and an optical bench to allow on-chip probing, quasi-optics coupling and over-the-air characterisation setups. The waveform generation module can generate CW and wideband high-speed complex waveforms (>40 GHz) to meet the requirements of future communications for frequencies up to 1.1 THz. The signal analysis module can perform spectrum analysis of signal sources as well as real-time signal analysis on ultra-wideband, high data rate, complex signals in time domain for frequencies up to 1.1 THz. The device characterisation module permits continuous/pulsed current-voltage, network analysis and active load-pull measurements up to 1.1 THz. We are targeting measurements in hybrid transmission systems of several hundred Gigabits per second (Gbit/s). To allow other external groups and industry to use this unique measurement system for their research and development, a key aspect of the new measurement system is the possibility for remote control of all parameters via the Internet, which will enable use of the measurement system without the need to move the measurement system around and allow remote access to real-time data.

The rapid growth of the rich variety of connected devices, from sensors, to cars, to wearables, to smart buildings, is placing a varied and highly complex set of bandwidth, latency, priority, reliability, power, roaming, and cost requirements on how these devices connect and on how information is moved around. Efficient communications remains a very difficult challenge for our digital world, and understanding how to design devices and systems that make good trade-offs between these different requirements requires skills from several disciplines. MANGI will underpin the critical mass and expertise in Bristol's Smart Internet and Devices Laboratory (SIDL) enabling the creation of a Next Generation Internet, with career development of our senior and most talented postdoctoral researchers forming a core part of our activity. Bristol's SIDL brings together the Smart Internet Lab (SIL) in Electrical & Electronic Engineering and the Centre for Device Thermography and Reliability (CDTR) in Physics at the University of Bristol, and has a world-leading track record, spanning the complete digital communication engine from novel wide bandgap semiconductor RF/optical devices to state-of-the-art high performance network architecture design and operation, on the pathway to enabling the Next Generation Internet. New devices and materials are critically needed as key enablers for the necessary transition from the current to the Next Generation Internet which needs to be energy efficient and provide highly flexible connectivity across optical-wireless domains. Using pump-priming projects to retain and develop our outstanding postdoctoral researchers, revolutionary interdisciplinary approaches will be developed in order to adopt high risk strategies focused on grand challenges aimed at enabling the Next Generation Internet. This approach taken is not possible with standard mode funding. Advances in component technologies, to provide higher speed/linearity, higher power devices, more compact device and packaging design, alongside use of new materials will have transformative impact upon network operation. The flexibility of the platform will be a corner stone of MANGI, allowing our most senior postdoctoral researchers to develop and drive their own research ideas, with interdisciplinary mentoring by senior members of SIDL and industry. This will help remove blockages in current technology and overcome the current internet infrastructure challenges. Standard research paths are not able to support independent development and innovation at physical and network layer functionalities, protocols, and services, while at the same time supporting the increasing bandwidth demands of changing and diverse applications, largely because of current limitations in semiconductor device and packaging technology and a lack of co-design of the multitude of constituent parts.