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ECP

Country: France
2 Projects, page 1 of 1
  • Funder: European Commission Project Code: 662338
    Overall Budget: 177,732,000 EURFunder Contribution: 31,816,400 EUR

    The SeNaTe project is the next in a chain of thematically connected ENIAC JU KET pilot line projects which are associated with 450mm/300mm development for the 12nm and 10nm technology nodes. The main objective is the demonstration of the 7nm IC technology integration in line with the industry needs and the ITRS roadmap on real devices in the Advanced Patterning Center at imec using innovative device architecture and comprising demonstration of a lithographic platform for EUV and immersion technology, advanced process and holistic metrology platforms, new materials and mask infrastructure. A lithography scanner will be developed based on EUV technology to achieve the 7nm module patterning specification. Metrology platforms need to be qualified for N7’s 1D, 2D and 3D geometries with the appropriate precision and accuracy. For the 7nm technology modules a large number of new materials will need to be introduced. The introduction of these new materials brings challenges for all involved processes and the related equipment set. Next to new deposition processes also the interaction of the involved materials with subsequent etch, clean and planarization steps will be studied. Major European stakeholders in EUV mask development will collaboratively work together on a number of key remaining EUV mask issues. The first two years of the project will be dedicated to find the best options for patterning, device performance, and integration. In the last year a full N7 integration with electrical measurements will be performed to enable the validation of the 7nm process options for a High Volume Manufacturing. The SeNaTe project relates to the ECSEL work program topic Process technologies – More Moore. It addresses and targets as set out in the MASP at the discovery of new Semiconductor Process, Equipment and Materials solutions for advanced CMOS processes that enable the nano-structuring of electronic devices with 7nm resolution in high-volume manufacturing and fast prototyping.

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  • Funder: European Commission Project Code: 826589
    Overall Budget: 126,895,000 EURFunder Contribution: 29,382,500 EUR

    The metrology domain (which could be considered as the ‘eyes and ears’ for both R&D&I and production) is a key enabler for productivity enhancements in many industries across the electronic components and system (ECS) value chain and have to be an integral part of any Cyber Physical Systems (CPS) which consist of metrology equipment, virtual metrology or Industrial internet of things (IIoT) sensors, edge and high-performance computing (HPC). The requirements from the metrology is to support ALL process steps toward the final product. However, for any given ECS technology, there is a significant trade-off between the metrology sensitivity, precision and accuracy to its productivity. MADEin4 address this deficiency by focusing on two productivity boosters which are independent from the sensitivity, precision and accuracy requirements: • Productivity booster 1: High throughput, next generation metrology and inspection tools development for the nanoelectronics industry (all nodes down to 5nm). This booster will be developed by the metrology equipment’s manufacturers and demonstrated in an industry 4.0 pilot line at imec and address the ECS equipment, materials and manufacturing major challenges (MASP Chapter 15, major challenges 1 – 3). • Productivity booster 2: CPS development which combines Machine Learning (ML) of design (EDA) and metrology data for predictive diagnostics of the process and tools performances predictive diagnostics of the process and tools performances (predictive yield and tools performance). This booster will be developed and demonstrated in an industry 4.0 pilot line at imec, for the 5nm node, by the EDA, computing and metrology partners (MASP Chapter 15, major challenge 4). The same CPS concept will be demonstrated for the ‘digital industries’ two major challenges of the nanoelectronics (all nodes down to 5nm) and automotive end user’s partners (MASP Chapter 9, major challenges 1and 3).

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