In recent years, Artificial Intelligence has shifted towards collaborative learning paradigms, where multiple systems acquire and elaborate data in real-time and share their experience to improve their performance. MEMRINESS will generate new fundamental computing primitives that will overcome the current challenges for the deployment of intelligent systems on the edge. The requirements of a system operating on the edge are very tight: power efficiency, low area occupation, fast response times, and online learning. Brain-inspired architectures such as Spiking Neural Networks (SNNs) use artificial neurons and synapses that perform low-latency computation and internal-state storage simultaneously with very low power consumption, but at present they mainly rely on standard technologies, which make SNNs unfit to meet the above-mentioned constraints. Indeed, the dream of compact and efficient neurons and synapses, able to work at different time scales to match real-time constants and to retain memory of their state even in the absence of a power supply, cannot be realised without flanking standard technologies with emerging ones. In this respect, memristive technology has shown promising results, due to its ability to support non-volatile storage of the SNN parameters. Yet so far, research has prioritised the non-volatile properties of the devices rather than focusing additionally on the reproduction of multi-temporal synaptic and neural dynamics. To solve this problem, I will develop neurons and synapses that exploit the intrinsic physical characteristics and dynamics of volatile and non-volatile memristive devices to enable the design of compact, power efficient SNNs with multi timescale dynamics. I will use a holistic approach and co-develop every aspect, from the devices to the circuits, to the learning algorithms. I will use the results to design a SNN and demonstrate its collaborative and online learning capabilities in three scenarios of increasing complexity.

The Ferro4EdgeAI project will provide an ultra-low power, scalable edge accelerator for artificial intelligence incorporating a memory augmented neural network, based on low cost, high density, multi-level, Back End of Line (BEoL) integrated ferroelectric (FE) technology. We expect to achieve a 2500x gain in energy-efficiency to break the POPS/W barrier with respect to the state-of-the-art CMOS accelerators and predictions for other emerging technology AI hardware. To do so, five ambitious specific objectives have been selected: - multi-level functionality in hafnia-based thin films by investigating the optimum trade-off in memory window, film thickness & stability of the ferroelectric state - low operating voltage for the non-volatile memory and robust multilevel operation of the FeFET-2 for high density logic operations and data storage. A low operating voltage is mandatory for power rating reduction, while robust multilevel operation is essential for analogue in-memory computing at the edge. - integration and characterization of multi-level, low voltage, FeFET-2 arrays - definition, design and demonstration of a low power FE AI accelerator suitable for scalable systems integration - Systems simulation of ultra-low power FE accelerator enhanced edge processing for targeted edge applications of voice and image recognition Ferro4EdgeAI is a multidisciplinary project engaging 12 partners from 6 countries covering the academic and industrial worlds (including 2 SMEs). An implementation plan is presented in the form of 6 work packages, 5 of which are technical in nature. Synergy in communication and dissemination by the several partners and stakeholders (including an external advisory board and collaboration with South Korea) will maximize the project progress and impact. Solutions to overcome the fundamental technological barriers as well as appropriate deliverables, tasks, milestones, and risks to complete the project objectives in due time are presented.

In the context of the fourth industrial revolution along with unprecedented growing global interdependencies, an innovative, inclusive and sustainable society is a sound European priority. For many people, the way towards inclusive and sustainable daily life goes through a lightweight in-ear device allowing speech-to-speech translation. Today, such IoT devices require internet connectivity which is proven to be energy inefficient. While machine translation has greatly improved, an embedded lightweight energy-efficient hardware remains elusive because existing solutions based on artificial neural networks (NNs) are computation-intensive and energy-hungry requiring server-based implementations, which also raises data protection and privacy concerns. Today, 2D electronic architectures suffer from "unscalable" interconnects, making it difficult for them to compete with biological neural systems in terms of real-time information-processing capabilities with comparable energy consumption. Recent advances in materials science, device technology and synaptic architectures have the potential to fill this gap with novel disruptive technologies that go beyond conventional CMOS technology. A promising solution comes from vertical nanowire field-effect transistors (VNWFETs) to unlock the full potential of truly 3D neuromorphic computing performance and density. Through actual VNWFETs fabrication setting up a design-technology co-optimization approach, the FVLLMONTI vision is to develop regular 3D stacked hardware layers of NNs empowering the most efficient machine translation thanks to a fine-grain hardware / software co-optimisation. FVLLMONTI consortium is a strong partnership with complementary expertise and extensive track-records in the fields of nanoelectronics, unconventional logic design, reliability, system‐level design, machine translation, cognition sciences. The consortium is composed of 50% of junior researchers and 90% of first-time participants to FETPROACT.

Our main objective is the development of a reconfigurable platform to accommodate both for a generic sensor interface as well as a dedicated sensor transducer element. The tunable analog front-end (AFE) interface should be enabled at the fine-grain level by emerging reconfigurable field effect transistor (RFET) and negative differential resistance (NDR) transistor technologies that provide co-integration capabilities with European 22nm CMOS processing technologies allowing for a More-than-Moore sensor technology approach. Being doping-free these two key enabling technologies provide a high potential gain for a large variety of sensor system requiring a low 1/f noise behavior ranging from solid-state sensors, such as photodiodes, to environmental monitoring for the automotive market, and physiological signal monitoring, such as cancer detection. Having naturally un-gated channel areas, reconfigurable field effect transistors are the perfect target vehicle for functionalized surfaces, e.g. for the detection of colorectal cancer (CRC) biomarkers, serving as a Reconfigurable Sensor Transducer (RST) for the healthcare sector. Together with the AFE, these transducers can be integrated into a CMOS as a use-case demonstration of the flexible platform. To sum up, in SENSOTERIC we will investigate smart sensing solutions in environmental monitoring and healthcare, where both the RST and the AFE utilize the capabilities of emerging RFET and NDR key enabling technologies.

In a multi-disciplinary approach, FIXIT aims at the development of a disruptive, ferroelectric ultra-low power memory and computing technology, fostering the hardware implementation of novel AI-driven electronic systems. Ferroelectricity is the most energy-efficient non-volatile storage technology. FIXIT leverages two recent European discoveries of CMOS compatible ferroelectric materials: ferroelectric HfO2 as first reported in 2011 by NaMLab – the coordinator of FIXIT, and ferroelectric wurtzite AlScN discovered by the Project partner CAU in 2019. Our major goal is the scaling of ferroelectric synaptic devices to the <20nm regime while maintaining their analogue and multi-level switching properties. Moreover, we aim at the integration of these scaled devices into ultra-dense crossbar arrays featuring non-volatile multi-bit digital functionality and highly parallel multiply and accumulate operations, representing the synaptic interconnects calculation at the heart of AI-algorithms. In our consortium we build on the vast, interdisciplinary, and complementary expertise of the 11 project partners (3 industries, 1 SME, 4 universities, 3 RTOs) covering know-how on material, process and device development, CMOS integration, equipment and manufacturing, physical and electrical characterization, TCAD modelling, packaging, circuit design and system integration. Pushing European research in this topic will sustain the first-mover advantage and contribute to the European industry capability to provide advanced circuits for its needs. This is in-line with the European Chips Act, where the Commission has identified technological leadership in semiconductor technologies as indispensable for European digital sovereignty, and decided to support the field with large investments. FIXIT will also support Europe’s competitiveness in semiconductors with a systematic outreach to students, the training of young researchers and the building of international cooperation.