The overall objective of the PIn3S project is to realize Pilot Integration of 3nm Semiconductor technology. This covers Process Integration, creation of Lithography Equipment, EUV Mask Repair Equipment and Metrology tools capable to deal with 3D structures, defects analysis, overlay and feature size evaluation. Each of these objectives will be achieved by cooperation between key European equipment developers like; ASML, Zeiss, Thermo Fisher, Applied Materials, Nova, KTI involved with their suppliers, involvement of a strong knowledge network based on Universities of Germany, Heidelberg University Hospital, and the Netherland, TU Delft and the University of Twente, complemented with key Technology Institutes such as imec and Fraunhofer. The project addresses Section 15 “Electronics Components & Systems Process Technology, Equipment, Materials and Manufacturing”, Major Challenge 4 “Maintaining world leadership in Semiconductor Equipment, Materials and Manufacturing solutions” and Major Challenge 1 “Developing advanced logic and memory technology for nanoscale integration and application-driven performance” of the ECSEL JU Annual Work Plan 2018. As set out in the Multi Annual Strategic Plan 2018, PIn3S addresses the ambition for the European Equipment & Manufacturing industry for advanced semiconductor technologies to lead the world in miniaturization by supplying new equipment and materials approximately two years ahead of introduction of volume production of advanced semiconductor manufacturers. With the results of the Pin3S project the consortium builds on realizing IC manufacturers to migrate to the 3nm Technology node which enables a class of new products which have more functionality, more performance and are more power efficient. As such it will form the bases for innovations yet to come enabling solutions that address the societal challenges in communication, mobility, health care, security, energy and safety & security.

R3-POWERUP will push through the new generation of 300mm Pilot Line Facility for Smart Power technology in Europe. This will enable the European industry to set the world reference of innovative and competitive solutions for critical societal challenges, like Energy saving and CO2 Reduction (ref. to COP21 Agreement ), as well as Sustainable Environment through electric mobility and industrial power efficiency. ● Development and demonstration of a brand new 300mm advanced manufacturing facility addressing a multi-KET Pilot Line (i.e. Nanoelectronics, Nanotechnology, Advanced Manufacturing) ● Improvement in productivity and competitiveness of integrated IC solutions for smart power and power discrete technologies. The strategy of the project is the following: ● The Pilot Line will enable the realization of sub-100nm Smart Power processes, starting from the 90nm BCD10 process, taking profit from the advanced and peculiar equipments available only for 300mm wafer size. ● The availability of a 300mm full processing line will also exploit the portability to 300mm of the most critical and expensive process steps devoted to power discrete devices. ● The Pilot Line will build on Digital Factory and Industry 4.0 principles, enforcing a flexible, adaptive and reliable facility, in order to investigate also the synergy and economic feasibility of supporting both Smart Power and power discrete processes in the same manufacturing line. ● The application of such technologies will be a breakthrough enabler for Energy Efficiency and CO2 Reduction worldwide, in line with COP21’s global action plan. The Pilot Line is based on three main pillars: 1. Market driven continuous innovation on smart-power and power discrete; 2. Industrial policy focused on high quality and mass production’s cost optimization; 3. Set the ground for future wafer upgrade of “More than Moore” disruptive technologies (e.g. advanced MEMS manufacturing, now at 200mm)

The SeNaTe project is the next in a chain of thematically connected ENIAC JU KET pilot line projects which are associated with 450mm/300mm development for the 12nm and 10nm technology nodes. The main objective is the demonstration of the 7nm IC technology integration in line with the industry needs and the ITRS roadmap on real devices in the Advanced Patterning Center at imec using innovative device architecture and comprising demonstration of a lithographic platform for EUV and immersion technology, advanced process and holistic metrology platforms, new materials and mask infrastructure. A lithography scanner will be developed based on EUV technology to achieve the 7nm module patterning specification. Metrology platforms need to be qualified for N7’s 1D, 2D and 3D geometries with the appropriate precision and accuracy. For the 7nm technology modules a large number of new materials will need to be introduced. The introduction of these new materials brings challenges for all involved processes and the related equipment set. Next to new deposition processes also the interaction of the involved materials with subsequent etch, clean and planarization steps will be studied. Major European stakeholders in EUV mask development will collaboratively work together on a number of key remaining EUV mask issues. The first two years of the project will be dedicated to find the best options for patterning, device performance, and integration. In the last year a full N7 integration with electrical measurements will be performed to enable the validation of the 7nm process options for a High Volume Manufacturing. The SeNaTe project relates to the ECSEL work program topic Process technologies – More Moore. It addresses and targets as set out in the MASP at the discovery of new Semiconductor Process, Equipment and Materials solutions for advanced CMOS processes that enable the nano-structuring of electronic devices with 7nm resolution in high-volume manufacturing and fast prototyping.