The 14AMI project is about creating technological solutions for the 14 Angstrom CMOS technology node, including a fully integrated functional CFET (Complementary Field Effect Transistor) as new active CMOS device, and state-of-the-art holistic metrology techniques for both wafer and mask inspection and review. All is aimed to keep the pace in the industry to follow “Moore’s law”. The project addresses the following 3 main pillars that are relevant in enabling manufacture of 14A technology, 1) lithography, 2) metrology and 3) process module integration. In lithography the aim is to realize solutions for the 0.55NA EUV scanner platform to secure 14Angstrom node compliance in performance, that is, resolution, alignment, throughput and optics lifetime. In Metrology the objective is to cover wafer and mask metrology and quality control. The aim is to develop holistic metrology, tools & methods and data analytics to improve overlay, CD and focus measurement and quality control with a Precision to Tolerance, P/T, ratio between 0.1 and 0.3. In process module integration work covers the realization and demonstration of a CFET – Complementary Field Effect Transistor - CMOS device. Three options will be investigated for integration; a monolithic, sequential and a hybrid solution. In addition, the partners will develop a PFAS-free photo resist to reduce the ecological footprint of photolithography processes, and a smart AI based sensor technology to improve vacuum chambers' efficiency and reduce waste. At societal level the expected impact of the 14AMI project will support the partners and their supplier network to stay at the leading edge of high-tech developments, crucial to meet the digitization challenges of the European society. Moreover, 14AMI will “boost industrial competitiveness”, and attract talent in Europe, while enabling new application in areas such as security, communication and enabling of further automation in mobility, health and research.

The objective of the 10ÅCe pThe objective of the 10ÅCe project is to explore and realize solutions for the 10Å CMOS chip technology. Its consortium covers the entire value chain for manufacturing of the CMOS chips in the 10A node, that is, from chip design to lithography to process technology and finally chip metrology. Essential parts of hardware, software and processing technology are developed pushing the boundaries of semiconductor design and manufacture to enable the new node and keep Moore’s law alive. The 10ÅCe project is built based on the following four pillars. Lithography Equipment: ASML and expert EUV partners Zeiss, FastMicro, IOM, Plasma Matters, TNO, TU/e, University of Twente and VDL-ETG will: • Increase key performance indicators of the EUV tool, to enable smaller pitches and increase yield. • Increase sustainability of the EUV tool, both during production as well as increasing the times a module in an EUV tool can be refurbished. Chip design and mask optimization: Imec with the involvement of expert imaging , CAD and IP design partners ARM, ASML and Siemens will: • Assess the impact of the introduction of 3D mCFET on chip design: in terms of power, performance and area. • Development of new computational lithography solutions to print 10Å CFET structures, to improve imaging by next generation mask design. Process Technology: As the ultimate device for logic, the CFET architecture is proposed and Imec and expert partners Coventor, EVG, IBS, Intel, JSR, LAM, RECIF, TEL, Zeiss and Wooptix will: • Demonstrate a fully functional monolithic CFET (mCFET) • Increase sustainability of the chip manufacturing process, across the manufacturing process and including resist material development. Process characterization: Applied Materials and expert partners Thermofisher, Nova, KLA and Bruker will: • Explore and realize high throughput and sample density per wafer, for the analysis, characterization for 10Å 3D CFET devices, interconnect and materials