The overall objective of the PIn3S project is to realize Pilot Integration of 3nm Semiconductor technology. This covers Process Integration, creation of Lithography Equipment, EUV Mask Repair Equipment and Metrology tools capable to deal with 3D structures, defects analysis, overlay and feature size evaluation. Each of these objectives will be achieved by cooperation between key European equipment developers like; ASML, Zeiss, Thermo Fisher, Applied Materials, Nova, KTI involved with their suppliers, involvement of a strong knowledge network based on Universities of Germany, Heidelberg University Hospital, and the Netherland, TU Delft and the University of Twente, complemented with key Technology Institutes such as imec and Fraunhofer. The project addresses Section 15 “Electronics Components & Systems Process Technology, Equipment, Materials and Manufacturing”, Major Challenge 4 “Maintaining world leadership in Semiconductor Equipment, Materials and Manufacturing solutions” and Major Challenge 1 “Developing advanced logic and memory technology for nanoscale integration and application-driven performance” of the ECSEL JU Annual Work Plan 2018. As set out in the Multi Annual Strategic Plan 2018, PIn3S addresses the ambition for the European Equipment & Manufacturing industry for advanced semiconductor technologies to lead the world in miniaturization by supplying new equipment and materials approximately two years ahead of introduction of volume production of advanced semiconductor manufacturers. With the results of the Pin3S project the consortium builds on realizing IC manufacturers to migrate to the 3nm Technology node which enables a class of new products which have more functionality, more performance and are more power efficient. As such it will form the bases for innovations yet to come enabling solutions that address the societal challenges in communication, mobility, health care, security, energy and safety & security.

The objective of the 3DAM project is to develop a new generation of metrology and characterization tools and methodologies enabling the development of the next semiconductor technology nodes. As nano-electronics technology is moving beyond the boundaries of (strained) silicon in planar or finFETs, new 3D device architectures and new materials bring major metrology and characterization challenges which cannot be met by pushing the present techniques to their limits. 3DAM will be a path-finding project which supports and complements several existing and future ECSEL pilot-line projects and is linked to the MASP area 7.1 (subsection More Moore). Innovative demonstrators and methodologies will be built and evaluated within the themes of metrology and characterization of 3D device architectures and new materials, across the full IC manufacturing cycle from Front to Back-End-Of-Line. 3D structural metrology and defect analysis techniques will be developed and correlated to address challenges around 3D CD, strain and crystal defects at the nm scale. 3D compositional analysis and electrical properties will be investigated with special attention to interfaces, alloys and 2D materials. The project will develop new workflows combining different technologies for more reliable and faster results; fit for use in future semiconductor processes. The consortium includes major European semiconductor equipment companies in the area of metrology and characterization. The link to future needs of the industry, as well as critical evaluation of concepts and demonstrators, is ensured by the participation of IMEC and LETI. The project will directly increase the competitiveness of the strong Europe-based semiconductor Equipment industry. Closely connected European IC manufacturers will benefit by accelerated R&D and process ramp-up. The project will generate technologies essential for future semiconductor processes and for the applications enabled by the new technology nodes.

R3-POWERUP will push through the new generation of 300mm Pilot Line Facility for Smart Power technology in Europe. This will enable the European industry to set the world reference of innovative and competitive solutions for critical societal challenges, like Energy saving and CO2 Reduction (ref. to COP21 Agreement ), as well as Sustainable Environment through electric mobility and industrial power efficiency. ● Development and demonstration of a brand new 300mm advanced manufacturing facility addressing a multi-KET Pilot Line (i.e. Nanoelectronics, Nanotechnology, Advanced Manufacturing) ● Improvement in productivity and competitiveness of integrated IC solutions for smart power and power discrete technologies. The strategy of the project is the following: ● The Pilot Line will enable the realization of sub-100nm Smart Power processes, starting from the 90nm BCD10 process, taking profit from the advanced and peculiar equipments available only for 300mm wafer size. ● The availability of a 300mm full processing line will also exploit the portability to 300mm of the most critical and expensive process steps devoted to power discrete devices. ● The Pilot Line will build on Digital Factory and Industry 4.0 principles, enforcing a flexible, adaptive and reliable facility, in order to investigate also the synergy and economic feasibility of supporting both Smart Power and power discrete processes in the same manufacturing line. ● The application of such technologies will be a breakthrough enabler for Energy Efficiency and CO2 Reduction worldwide, in line with COP21’s global action plan. The Pilot Line is based on three main pillars: 1. Market driven continuous innovation on smart-power and power discrete; 2. Industrial policy focused on high quality and mass production’s cost optimization; 3. Set the ground for future wafer upgrade of “More than Moore” disruptive technologies (e.g. advanced MEMS manufacturing, now at 200mm)

The overall objective of the IT2 project is to explore, develop and demonstrate technology options that are needed to realize 2nm CMOS logic technology extending the scaled Semiconductor technology roadmap to the next node in accordance to Moore’s law. These activities cover creation of Lithography equipment, new Processes & Modules and Metrology tools capable to create and deal with new 2nm node 3D structures, defect analysis, overlay and features. The topics addressed by the program relate to the ECSEL MASP 2019 Chapter 10; “Process Technology, Equipment, Materials and Manufacturing for electronic components and systems”, with emphasis on the following major challenge “the Extension of world leadership in Semiconductor Equipment, Materials and Manufacturing solutions” and “Developing Technology for heterogeneous System-on-Chip (SoC) Integration” of the ECSEL JU Annual Work Plan 2019. The relation of the IT2 project to world leadership regards the extension of the scaled semiconductor technology roadmaps and thereby maintain competence in advanced More Moore technology in Europe to support leading edge manufacturing. The relation of the IT2 project to the Developing Technology for heterogeneous System-on-chip Integration comes from activities regarding “System Scaling” in which technology is developed that enables wafer-to-wafer bonding creating 3D heterogeneous solutions with the aim to resolve performance limitations in power and data congestion. In regard to the annual work plan 2019, the IT2 project support the ECSEL JU objectives by contribution to the development of a strong and competitive Electronic Components and Systems (ECS) by involving many of the equipment and tool developers like; ASML, Zeiss, Thermo Fisher, Applied Materials, Nova, KLA along the value chain and knowledge institutes such as ARCNL, imec, PTB, TNO and TU/e. And by stimulating a dynamic ecosystem through through the involvement of SMEs like IBS, Recif, Reden and Unity.