In line with industry needs, Moore’s law, scaling in ITRS 2013, and ECSEL JU MASP 2017, the main objective of the TAPES3 project is to discover, develop and demonstrate lithographic, metrology, EUV mask technology, devices and process modules enabling 3nm node technology. This is planned with available EUV/NA 0.33 scanners, and with system design and integration of a new hyper NA EUV lithography tool to enable more single exposure patterning at 3nm to create complex integrated circuits. Process steps for 3D devices as alternative to the conventional FINFet will be explored for application in the 3nm node. The impact of the application of these so called 3D devices on circuit topology and logic design will be explored. During the development, specific challenges in metrology for the characterization of 3D devices will be assessed and metrology tools will be newly developed. The result will be demonstrated in the imec pilot line. The TAPES3 project relates to the ECSEL work program topic Equipment, Material and Manufacturing. It addresses and targets, as set out in MASP, the grand Challange of "More Moore Equipment and Materials for sub 10nm technologies" by exploring the requirements and solutions for the 3nm node. The project touches the core of the continuation of Moore’s law. Moreover, the cost aware development process will support the involved companies, and will place them in a preferred position over their worldwide competition. Through their worldwide affiliations, the impact of the TAPES3 project will be felt outside Europe in America and Asia Pacific semiconductor centers and is expected to benefit the European economy a lot by supporting its semiconductor equipment and metrology sectors with innovations, exports and employment.

The objective of the 10Ce pThe objective of the 10Ce project is to explore and realize solutions for the 10 CMOS chip technology. Its consortium covers the entire value chain for manufacturing of the CMOS chips in the 10A node, that is, from chip design to lithography to process technology and finally chip metrology. Essential parts of hardware, software and processing technology are developed pushing the boundaries of semiconductor design and manufacture to enable the new node and keep Moores law alive. The 10Ce project is built based on the following four pillars. Lithography Equipment: ASML and expert EUV partners Zeiss, FastMicro, IOM, Plasma Matters, TNO, TU/e, University of Twente and VDL-ETG will: Increase key performance indicators of the EUV tool, to enable smaller pitches and increase yield. Increase sustainability of the EUV tool, both during production as well as increasing the times a module in an EUV tool can be refurbished. Chip design and mask optimization: Imec with the involvement of expert imaging , CAD and IP design partners ARM, ASML and Siemens will: Assess the impact of the introduction of 3D mCFET on chip design: in terms of power, performance and area. Development of new computational lithography solutions to print 10 CFET structures, to improve imaging by next generation mask design. Process Technology: As the ultimate device for logic, the CFET architecture is proposed and Imec and expert partners Coventor, EVG, IBS, Intel, JSR, LAM, RECIF, TEL, Zeiss and Wooptix will: Demonstrate a fully functional monolithic CFET (mCFET) Increase sustainability of the chip manufacturing process, across the manufacturing process and including resist material development. Process characterization: Applied Materials and expert partners Thermofisher, Nova, KLA and Bruker will: Explore and realize high throughput and sample density per wafer, for the analysis, characterization for 10 3D CFET devices, interconnect and materials