The COMPASS project is a collaborative effort of AVL, Plansee, Nissan and Research Center Jülich to develop advanced SOFC APU systems for range extender applications in passenger cars. The consortium is perfectly integrated from powder-, cell-, stack-, APU system technology providers to vehicle manufacturer and an academic partner. The project will use innovative metal supports SOFC stack technology, which enables key features like rapid start up and mechanic robustness for this application. Within the project advanced APU systems will be developed with electrical efficiency above 50%, a start up time below 15min and a small packaging size suitable for integration into battery electrical vehicles. Under the lead of NISSAN also a prototype vehicle will be build up, where an APU system will be completely integrated into the electrical powertrain. A major focus of the project is technology validation and systematic durability/reliability development. Therefore in a specific workpackage all validation activities are concentrated. The validation testing includes tests on stack, APU system and vehicle level. The APU system will furthermore undergo automotive testing like vibration, altitude, climate chamber and salt spray. In an additional dedicated workpackage manufacturing cost and business case analyses will be performed. These analyses will help to reduce the technology cost by design-to-cost and design-to-manufacture measures and show the business case of this new powertrain concept compared to other alternative and conventional propulsion concepts. This project is worldwide the first approach to integrate SOFC APU systems into electrical powertrains and will help to significantly improve APU systems also for other applications like heavy duty trucks, marine and leisure/camping.

The 14AMI project is about creating technological solutions for the 14 Angstrom CMOS technology node, including a fully integrated functional CFET (Complementary Field Effect Transistor) as new active CMOS device, and state-of-the-art holistic metrology techniques for both wafer and mask inspection and review. All is aimed to keep the pace in the industry to follow “Moore’s law”. The project addresses the following 3 main pillars that are relevant in enabling manufacture of 14A technology, 1) lithography, 2) metrology and 3) process module integration. In lithography the aim is to realize solutions for the 0.55NA EUV scanner platform to secure 14Angstrom node compliance in performance, that is, resolution, alignment, throughput and optics lifetime. In Metrology the objective is to cover wafer and mask metrology and quality control. The aim is to develop holistic metrology, tools & methods and data analytics to improve overlay, CD and focus measurement and quality control with a Precision to Tolerance, P/T, ratio between 0.1 and 0.3. In process module integration work covers the realization and demonstration of a CFET – Complementary Field Effect Transistor - CMOS device. Three options will be investigated for integration; a monolithic, sequential and a hybrid solution. In addition, the partners will develop a PFAS-free photo resist to reduce the ecological footprint of photolithography processes, and a smart AI based sensor technology to improve vacuum chambers' efficiency and reduce waste. At societal level the expected impact of the 14AMI project will support the partners and their supplier network to stay at the leading edge of high-tech developments, crucial to meet the digitization challenges of the European society. Moreover, 14AMI will “boost industrial competitiveness”, and attract talent in Europe, while enabling new application in areas such as security, communication and enabling of further automation in mobility, health and research.

In the ID2PPAC project the technology solutions for the 2nm node identified in the preceding project IT2 will be consolidated and integrated with the objective to demonstrate that Performance Power Area and Cost (PPAC) requirements for this generation of leading edge logic technology can be achieved. To continue the Moore’s law trajectory to the 2nm node, while meeting PPAC requirements, the combination of further advancements in EUV lithography & masks, 3D device structures, materials and metrology is required. The strength of the project pivots on the focused engagement of leading expert partners in these key interlocking areas and a shared pilot line. The ID2PPAC project, is expected to enable IC-fabs to do EUV-based, single-print, High Volume Manufacturing for the 2nm node by 2025. This technology evolution is driven by the growing demand for compute power which increases more than exponentially with time and has made the world migrate from 1 billion interconnected devices in the “PC era” to 10 billion in the “Mobile + cloud era” to the future “Intelligence era” in which there will be over 100 billion intelligent connected devices. To enable this growth, the semiconductor industry is continuously pursuing technology innovations to realize this progress as has been predicted by Moore’s Law and will continue to do so. The project will also help to expand Europe's technological capacity to act in this field, which is crucial for digitization, (edge) AI and for solving national, European and global societal challenges and will strengthen the consortium of leading European companies and institutes active in this sector.