Semi-insulating silicon substrates would be very attractive as handle wafers in Silicon On Insulator (SOI) technologies because they would provide very low-absorption substrates for RF and monolithic microwave integrated circuits. Two of the investigators have previously theoretically analysed the effect of different deep level impurities on silicon resistivity and shown that a resistivity of nearly 100kOhm.cm should be achievable by dopant compensation. This theoretical work has been supported by our recently published experimental feasibility study that has delivered a very promising resistivity value of 12kohm.cm using Mn as the deep level impurity. This proposal aims to study the science and engineering of high resistivity silicon substrates for high frequency integrated circuits. The team encompasses expertise on the materials science of deep level impurities (University of Oxford), on the physics and technology of high frequency silicon devices (University of Southampton), on silicon wafer growth (MEMC) and on the design and fabrication of high frequency integrated circuits (Zarlink). The project aims to better understand the diffusion and doping vs resistivity relations of appropriate deep level impurities (including Mn), and hence to maximise the resistivity of the silicon handle wafer. Contamination issues arising from the deep level impurities will be addressed by investigating diffusion barriers and also by developing a back-end processing approach that takes advantage of the high diffusivity of some deep level impurities. The recent incorporation of Cu metallization into back-end silicon production processes suggests that other deep level impurities would not be seen by industry as a major contamination issue in back-end processing. Finally, SOI wafers will be fabricated on semi-insulating silicon substrates and detailed high frequency characterisation carried out.

Silicon on Insulator (SOI) technology is now of critical importance to future generations of integrated circuit chips. SOI offers potentially faster chip operation, simplified manufacturing technology and low power operation. It also offers the possibility of integrating entire electronic systems on a chip. Very novel variations on this relatively simple substrate are emerging. The Silicon on Silicide on Insulator (SSOI) substrate is one such substrate. This substrate includes a low resistivity layer (tungsten silicide) buried under the active silicon. Primary applications of this layer would be as ohmic contacts and for lateral current flow of current prior to return to surface contacts. ICs use buried ion implanted layers for this function but the silicide offers 2 orders of magnitude reduction in series resistance. Parasitic resistance in bipolar and power devices can therefore be substantially reduced by employing this substrate. The SSOI offers further potential advantage which has not yet been exploited. The buried silicide is polycrystalline in structure and diffusion of common dopants for silicon will therefore be by grain boundary diffusion which will be rapid. Low thermal budget treatment may be used to move these dopants relatively long distance without disturbance of other dopant profiles in the overlying silicon. Short time rapid thermal anneal can then be employed to out diffuse dopant from the silicide to produce ultra-shallow junctions in the silicon. This can all be achieved at the near back end of the device production ensuring tight control of all junction profiles, elimination of wide buried implanted layers and simplification in the manufacturing schedule. This technology will provide further opportunity for exciting new process and device architectures with advantage offered in unit cost and electronic device performance over the spectrum from ICs and microwave devices to power and smart power transistors. The focus of this contract is therefore to conduct a detailed scientific investigation of dopant diffusion in tungsten silicide. Sensitive electronic experimental structures will be employed which will allow accurate characterisation of dopant diffusion over distance. This is vitally important to provide the diffusivity data, segregation coefficients etc which will allow design of future processes and devices. Strategy for supply of dopant to the buried silicide layer must also be developed. For near back end of processing technology this will require variations on refilled trench technology. This project will seek to investigate this approach using a number of refill materials. The technology will lead to ultra low parasitic resistance. It is therefore proper to ensure that any trench refill technology may offer low additional resistance. Trench refill with tungsten will therefore be undertaken to provide an optimised substrate for power devices and linear ICs. The potential of the technology will be demonstrated with a relatively simple microwave diode. The diode will be manufactured on the SSOI substrate and will exhibit minimised parasitic capacitance and resistance. Exploitation of the substrate and the proposed technology can develop in new contracts or industrial collaborations during the time of the project to address smart power/ vertical power devices, linear IC technology and high frequency components.

Semi-insulating silicon substrates would be very attractive as handle wafers in Silicon On Insulator (SOI) technologies because they would provide very low-absorption substrates for RF and monolithic microwave integrated circuits. Two of the investigators have previously theoretically analysed the effect of different deep level impurities on silicon resistivity and shown that a resistivity of nearly 100kOhm.cm should be achievable by dopant compensation. This theoretical work has been supported by our recently published experimental feasibility study that has delivered a very promising resistivity value of 12kohm.cm using Mn as the deep level impurity. This proposal aims to study the science and engineering of high resistivity silicon substrates for high frequency integrated circuits. The team encompasses expertise on the materials science of deep level impurities (University of Oxford), on the physics and technology of high frequency silicon devices (University of Southampton), on silicon wafer growth (MEMC) and on the design and fabrication of high frequency integrated circuits (Zarlink). The project aims to better understand the diffusion and doping vs resistivity relations of appropriate deep level impurities (including Mn), and hence to maximise the resistivity of the silicon handle wafer. Contamination issues arising from the deep level impurities will be addressed by investigating diffusion barriers and also by developing a back-end processing approach that takes advantage of the high diffusivity of some deep level impurities. The recent incorporation of Cu metallization into back-end silicon production processes suggests that other deep level impurities would not be seen by industry as a major contamination issue in back-end processing. Finally, SOI wafers will be fabricated on semi-insulating silicon substrates and detailed high frequency characterisation carried out.

Wireless Body Area Networking (WBAN) is an important area of emerging technology where a network of bodyworn or personal electronic devices is established, most often using radio communications. A WBAN may also have to support person-person or wider area communications. Therefore, a WBAN is an important and challenging environment for bodyworn antennas since they may be required to support or be configured to yield quite distinct propagating modes such as: on-body only, off-body (e.g., cellular or wireless LAN) only, or some combination of these. In addition, an ideal antenna for WBAN use will be low profile or conformal, efficient with minimal power losses in body tissues and not adversely affected by the user's movements. This work will address these challenges directly by creating and investigating a new class of wideband low-profile patch-antenna elements with reduced groundplane currents (higher efficiency and greater safety) and with a tangential propagating mode for both over the body surface communications. The tangential propagating mode also has the potential for achieving omnidirectional coverage from one antenna element depending on the operating frequency, albeit with additional losses in the through body direction. The achievement of these aims will involve detailed work in the area of patch element design, the use of advanced dielectric materials and will leverage the latest research on electromagnetic metamaterials. Although the work will focus on antennas for the 2.4 GHz industrial, scientific and medical (ISM) band, consideration will be given to lower frequencies down to 400 MHz in support applications such as medical device networking. The project will use both theoretical and numerical analysis and the funding requested will allow the experimental validation of the work, specifically in terms of whole body radiation efficiency measurements and radio-over-fibre measurements of on-body antenna element coupling.