The Mont-Blanc 2020 (MB2020) project ambitions to initiate the development of a future low-power European processor for Exascale. MB2020 lays the foundation for a European consortium aiming at delivering a processor with great energy efficiency for HPC and server workloads. A first generation product is scheduled in the 2020 time frame. Our target is to reach exascale-level power efficiency (50 Gflops/Watt at processor level) with a second generation planned for 2022. Therefore, we will, within MB2020: 1. define a low-power System-on-Chip (SoC) implementation targeting Exascale, with built-in security and reliability features; 2. introduce strong innovations to improve efficiency with real-life applications and to outperform competition (vector instruction implementation, memory latency and bandwidth, power management, 2.5D integration); 3. develop key modules (IPs) needed for this implementation; 4. provide a working prototype demonstrating MB2020 key components and system level simulations, with a co-design approach based on real-life applications; 5. explore the reuse of these building blocks to serve other markets than HPC. Our key choices are: a) To use the ARM ISA (Instruction Set Architecture) because its has strong technological relevance and it offers a dynamic ecosystem, which is needed to deliver the system software and applications mandatory for successful market acceptance. b) To design, implement or leverage new technologies (Scalable Vector Extension, NoC, High Bandwidth Memory, Power Management, …) as well as innovative packaging technologies to improve the versatility, performance, power efficiency, reliability, and security of the processor. c) To improve on the economic sustainability of processor development through a modular design that allows to retarget our SoC for different markets.

The main goal of Rising STARS is to enable a parallel programming framework for the development and execution of advanced large-scale Cyber Physical Systems (CPS) with High Performance Computing (HPC) and real-time requirements. Overall, there is an urgent necessity to develop run-time parallel frameworks, compatible with HPC, capable of guaranteeing that decisions made at run-time maintains the guarantees about system correctness and timing behavior. These new run-time capabilities however, cannot preclude the ability of run-times to dynamically adapt the execution to new working conditions or changing modes of operation of CPS to maximise the utilisation and performance capabilities of parallel heterogeneous architectures. A key element of the Rising STARS framework will be the incorporation of a unified, efficient and highly configurable data acquisition strategy fully integrated in the parallel programming models with the objective of improving productivity in CPS software development. Exposing the data-acquisition to the programmer (by including it into the parallel programming model) is also key to overlap data-transfers with computation. Another objective of the project is to add this capability in existing programming models for HPC and to investigate new parallel programming extensions to allow developers to define the real-time properties of the system in terms of periodicity and timing constraints. Finally, one of our main objectives is to implement several demonstration platforms to promote the main technological developments of this R&I action and their performance under realistic conditions, including Adaptive Optics for giant telescopes and SSA experiments, data processsing for SKA, and critical real-time embedded systems.

ExaNoDe will investigate, develop integrate and validate the building blocks (technology readiness level 5) for a highly efficient, highly integrated, multi-way, high-performance, heterogeneous compute element aimed towards exascale computing. It will build on multiple European initiatives for scalable computing, utilizing low- power processors and advanced nanotechnologies. ExaNoDe will draw heavily on the Unimem memory and system design paradigm defined within the EUROSERVER FP7 project, providing low-latency, high-bandwidth and resilient memory access, scalable to Exabyte levels. The ExaNoDe compute element aims towards exascale compute goals through: • Integration of the most advanced low-power processors and accelerators (across scalar, SIMD, GPGPU and FPGA processing elements) supported by research and innovation in the deployment of associated nanotechnologies and in the mechanical requirements to enable the development of a high-density, high-performance integrated compute element with advanced thermal characteristics and connectivity to the next generation of system interconnect and storage; • Undertaking essential research to ensure the ExaNoDe compute element provides necessary support of HPC applications including I/O and storage virtualization techniques, operating system and semantically aware runtime capabilities and PGAS, OpenMP and MPI paradigms; • The development of a hardware emulation of interconnect to enable the evaluation of Unimem for the deployment of multiple compute elements and to leverage the potential of the ExaNoDe approach for HPC applications. Each aspect of ExaNoDe is aligned with the goals of the ETP4HPC. The work will be steered by first-hand experience and analysis of high-performance applications and their requirements; investigations being carried out with “mini-application” abstractions and the tuning of their kernels.

The COREnext project aims to build a computing architecture and digital components for sustainable and trustworthy B5G and 6G processing. This architecture must support an open, multi-vendor and multi-tenant disaggregated RAN by employing virtualization technology. A step forward in digital component design must be made to address the compute throughput and energy-efficiency requirements. This is addressed by the development of powerful and efficient heterogeneous accelerators, purpose-built for RAN computation and signal processing, as well as ultra-high-speed and low-power interconnects to support disaggregation of compute resources. A cornerstone of the project is trustworthiness. The pervasiveness of B5G and 6G use cases requires deeply embedded hardware trust anchors to fulfil the vision of secure disaggregated compute systems. To realize these goals, the project brings together major telecommunications and microelectronics players as well as academic research partners. A strategic roadmap will offer a transparent path towards future exploitation of the generated research results, fostering a continuing European strategy for the emergence of European digital capabilities in this communication-computing domain.