We wish to undertake research into communication centricmicroelectronic design methods which are in contrast to today'scomputation centric (or gate-level) techniques. We believe thatthis research is timely since electronics is at the cusp of change.For the last 60 years, digital gates have been costly to produce andhave limited performance. We are now entering an era where the wires,which were once almost free, becoming the cost and performancelimiter. This trend is well documented in the InternationalTechnology Roadmap for Semiconductors (ITRS) roadmap which clearlyidentifies the step change needed in circuits and associated designtechniques. They also identify spiralling design complexity,escalating power densities and associated thermal problems.We believe that networks-on-chip resolve many of the design challengesfor future nano CMOS implementation technologies. Our backgroundresearch in this area has already resulted in a low latencynetwork-on-chip architecture which we have fabricated on 180nm CMOS.This initial work focused on interconnect between a tiled processorarchitecture which we have been developing with MIT. However, forthis project we wish to go much further, looking at communication atmany levels and for a range of technologies, from ASIC design on CMOSchips through to new field programmable gate array (FPGA)architectures. FPGA architecture is a departure from our usual lineof research, so we have been particularly grantified to receivea fully funded PhD studentship from Altera UK (one of the two biginternational FPGA companies) who will collaborate with us on thisproject.

Energy efficiency is one of the primary design constraints for modern processing systems. Hardware accelerators are seen as a key technology to address the high performance with limited energy issue. In addition the arrival of computing languages such as OpenCL offer a route to the programmer to target different types of multi-core accelerators using a single source code. Performance portability is a significant challenge specially if the accelerators have different microarchitectures such as is the case in CPU-GPU-FPGA systems. This research addresses the energy and performance challenge by investigating how a device formed by processing units with different granularities ranging from coarse grain CPU cores of different complexity, medium grain general purpose GPU cores and fine grain FPGA logic cells can be dynamically programmed. The challenge is to be able to program all these resources with a single programming model and create a run-time system that can automatically tune the software to the best execution resource from energy and performance points of view. The results from this research are expected to deliver new fundamental insights to the question of: How future computers can obtain orders of magnitude higher performance with limited energy budgets?

During the past two decades, reliable wireless communication at near-theoretical-limit transmission throughputs has been facilitated by receivers that operate on the basis of the Bahl-Cocke-Jelinek-Raviv (BCJR) algorithm. Most famously, this algorithm is employed for turbo error correction in the Long Term Evolution (LTE) standard for cellular telephony, as well as in its previous-generation predecessors. Looking forward, turbo error correction promises transmission throughputs in excess of 1 Gbit/s, which is the goal specified in the IMT-Advanced requirements for next-generation cellular telephony standards. Throughputs of this order have only very recently been achieved by State-Of-the-Art (SOA) LTE turbo decoder implementations. However, this has been achieved by exploiting every possible opportunity to increase the parallelism of the BCJR algorithm at an architectural level, implying that the SOA approach has reached its fundamental limit. This limit may be attributed to the data dependencies of the BCJR algorithm, resulting in an inherently serial nature that cannot be readily mapped to processing architectures having a high degree of parallelism. Against this background, we propose to redesign turbo decoder implementations at an algorithmic level, rather than at the architectural level of the SOA approach. More specifically, we have recently been successful in devising an alternative to the BCJR algorithm, which has the same error correction capability, but does not have any data dependencies. Owing to this, our algorithm can be mapped to highly-parallel many-core processing architectures, facilitating an LTE turbo decoder processing throughput that is more than an order of magnitude higher than the SOA, satisfying future demands for gigabit throughputs. We will achieve this for the first time by developing a custom Field Programmable Gate Array (FPGA) architecture, comprising hundreds of processing cores that are interconnected using a reconfigurable Benes network. Furthermore, we will develop custom Network-on-Chip (NoC) architectures that facilitate different trade-offs between chip area, energy-efficiency, reconfigurability, processing throughput and latency. In parallel to developing these high-performance custom implementation architectures, we will apply our novel algorithm to both existing Graphics Processing Unit (GPU) and NoC architectures. This will grant us a rapid pace, allowing us to apply our novel algorithm to not only error correction, but to all aspects of receiver operation, including demodulation, equalisation, source decoding, channel estimation and synchronisation. Drawing upon our high-throughput algorithms and highly-parallel processing architectures, we will develop techniques for holistically optimising the algorithmic and implementational parameters of both the transmitter and receiver. This will facilitate practical high-performance schemes, which can pave the way for future generations of wireless communication. This research addresses key EPSRC priorities in the Information and Communication Technologies theme (http://www.epsrc.ac.uk/ourportfolio/themes/ict), including 'Many-core architectures and concurrency in distributed and embedded systems' and 'Towards an intelligent information infrastructure'. The 'Working together' priority is also addressed, since this cross-disciplinary research will develop new knowledge that spans the gap between high-performance communication theory and high-performance hardware design. This research will offer new insights into the design of many-core architectures, which the hardware design community will be able to apply in the design of general purpose architectures. Furthermore, the communication theory community will be able to apply our algorithms across even wider aspects of receiver operation.

There have not been many shake-ups in mainstream processor architectures, since von Neumann articulated their basic principles in 1945 and Hoff developed the microprocessor architecture in 1969. This is changing: field programmable technology has been adopted by major companies such as Microsoft and Intel for datacentre computing, and new architectures are expected which integrate processor cores and field programmable resources on the same chip. These developments are largely motivated by improvements in performance and energy efficiency of field programmable technology, which are so promising that industrial adoption takes place despite the significant challenge of developing applications for custom computing systems based on field programmable technology. Our vision is to address this challenge by advancing the foundation and applications of customisation, which involves developing hardware and software to fit design requirements. The proposed Platform project aims to pioneer new capabilities for enhancing design quality and designer productivity of custom computing systems, with potential to revolutionise many applications including those with needs for big data processing or for improved reliability and security. It builds on success of disruptive research funded by our previous Platform (EP/I012036/1). An example of such success is research in runtime reconfiguration of custom computing systems: we developed new analysis methods to enable reconfiguration to remove idle functions; we showed how reconfiguration can benefit many applications such as genomic data processing and finite-difference computation. Our work is disruptive since, in contrast to current focus on partial reconfiguration, it demonstrates that full reconfiguration can provide significant energy-efficient acceleration over conventional multicore and manycore processors reducing, for example, runtime of Bisulfite sequence alignment from hours to minutes for non-invasive prenatal and cancer diagnosis. Moreover, we invented the first field programmable architecture capable of single-cycle on-chip configuration generation, while current commercial devices are based on off-chip configuration generation that can take hours. Such exciting progress is only possible because the Platform Grant enabled high-risk research by researchers who would otherwise suffer from funding gaps: 12 Research Associates in our team enjoyed Platform support before they found permanent positions. Renewed Platform support will allow continuing development of our dynamic and ambitious research team to explore next-generation computer systems and their applications. The flexibility of the renewed Platform Grant will be used to address three new strategic areas, on which we are uniquely capable of making major impacts; we will conduct exploratory research to identify promising projects for responsive mode or other forms of funding: 1. Multi-level tradeoff-aware design automation, which includes investigating customisation strategies and the associated tradeoffs, automation of effective customisation strategies, and developing reusable demonstration facilities and testbeds. 2. Reconfigurable big data and cloud architectures, which include customisable big data processing, runtime design generation and optimisation, and domain-specific cloud optimisation. 3. Reliable system development life cycle, which includes codesign of reliable and resilient systems, high-coverage testing and verification strategies, and reliability and resilience life cycle management. The added-value aspects for this Platform Grant proposal include: (a) ensuring a critical mass of researchers in key areas, (b) exploring significant strategic areas, (c) contributing to research infrastructure, (d) attracting fresh talents, (e) pioneering and strengthening international collaborations, and (f) accelerating technology transfer.

Advanced digital systems provide many exciting opportunities for UK economic growth. Our current Platform Grant has enabled us to implement a strategy of developing novel custom computing solutions, which involve customising the latest hardware and software elements, to meet demanding requirements from many applications. These include embedded systems applications such as software-defined radio and patient monitoring, as well as high-performance computing applications such as financial modelling and medical imaging. Continued Platform Grant funding will allow us to build on our success, to support strategic development of our team, and to extend our lead in custom computing technology to cover a wide variety of advanced digital systems for healthcare, environment, and security applications.There are three new strategic directions on which we are uniquely capable of making major impacts. We plan to conduct exploratory research to identify promising projects for responsive-mode funding for the following:1. customisable heterogeneous architectures, including design space exploration of devices and systems, relevant development methods and tools, and prototyping platforms and design portability enhancement;2. self-adapting design, including architecture innovations, adaptation policies and optimisation strategies, and design and verification flow;3. security-aware systems, including architecture enhancements, compilation and test generation environments, and experimental facilities and demonstration flow.The added value aspects for this Platform Grant proposal include: (a) providing continuity of support, (b) exploring significant strategic directions, (c) contributing to research infra-structure, (d) attracting fresh talents, (e) pioneering and strengthening international collaborations, and (f) accelerating technology transfer.