The objective of the 10Ce pThe objective of the 10Ce project is to explore and realize solutions for the 10 CMOS chip technology. Its consortium covers the entire value chain for manufacturing of the CMOS chips in the 10A node, that is, from chip design to lithography to process technology and finally chip metrology. Essential parts of hardware, software and processing technology are developed pushing the boundaries of semiconductor design and manufacture to enable the new node and keep Moores law alive. The 10Ce project is built based on the following four pillars. Lithography Equipment: ASML and expert EUV partners Zeiss, FastMicro, IOM, Plasma Matters, TNO, TU/e, University of Twente and VDL-ETG will: Increase key performance indicators of the EUV tool, to enable smaller pitches and increase yield. Increase sustainability of the EUV tool, both during production as well as increasing the times a module in an EUV tool can be refurbished. Chip design and mask optimization: Imec with the involvement of expert imaging , CAD and IP design partners ARM, ASML and Siemens will: Assess the impact of the introduction of 3D mCFET on chip design: in terms of power, performance and area. Development of new computational lithography solutions to print 10 CFET structures, to improve imaging by next generation mask design. Process Technology: As the ultimate device for logic, the CFET architecture is proposed and Imec and expert partners Coventor, EVG, IBS, Intel, JSR, LAM, RECIF, TEL, Zeiss and Wooptix will: Demonstrate a fully functional monolithic CFET (mCFET) Increase sustainability of the chip manufacturing process, across the manufacturing process and including resist material development. Process characterization: Applied Materials and expert partners Thermofisher, Nova, KLA and Bruker will: Explore and realize high throughput and sample density per wafer, for the analysis, characterization for 10 3D CFET devices, interconnect and materials

The overall objective of the IT2 project is to explore, develop and demonstrate technology options that are needed to realize 2nm CMOS logic technology extending the scaled Semiconductor technology roadmap to the next node in accordance to Moore’s law. These activities cover creation of Lithography equipment, new Processes & Modules and Metrology tools capable to create and deal with new 2nm node 3D structures, defect analysis, overlay and features. The topics addressed by the program relate to the ECSEL MASP 2019 Chapter 10; “Process Technology, Equipment, Materials and Manufacturing for electronic components and systems”, with emphasis on the following major challenge “the Extension of world leadership in Semiconductor Equipment, Materials and Manufacturing solutions” and “Developing Technology for heterogeneous System-on-Chip (SoC) Integration” of the ECSEL JU Annual Work Plan 2019. The relation of the IT2 project to world leadership regards the extension of the scaled semiconductor technology roadmaps and thereby maintain competence in advanced More Moore technology in Europe to support leading edge manufacturing. The relation of the IT2 project to the Developing Technology for heterogeneous System-on-chip Integration comes from activities regarding “System Scaling” in which technology is developed that enables wafer-to-wafer bonding creating 3D heterogeneous solutions with the aim to resolve performance limitations in power and data congestion. In regard to the annual work plan 2019, the IT2 project support the ECSEL JU objectives by contribution to the development of a strong and competitive Electronic Components and Systems (ECS) by involving many of the equipment and tool developers like; ASML, Zeiss, Thermo Fisher, Applied Materials, Nova, KLA along the value chain and knowledge institutes such as ARCNL, imec, PTB, TNO and TU/e. And by stimulating a dynamic ecosystem through through the involvement of SMEs like IBS, Recif, Reden and Unity.