In the post-Moore's law era, innovative new technologies to accelerate scientific computing and memory devices are growing explosively, amongst which photonic memory devices have been attracting a great amount of interest and hold future promise for built-in, non-volatile memory with high density, fast switching, multifunctionality, low-energy consumption, and multilevel data storage compared to electronic memory devices. It is now timely to ensure that these new device concepts are developed alongside new sustainable processes - as it is in the introduction stage of new products that manufacturing processes can also be changed. Current manufacturing of high-resolution semiconductor devices primarily relies on photolithography as the patterning technique of choice. During the fabrication of these resist-based lithography techniques, development and lift-off steps utilize alkaline solutions and organic solvents as developers and removers. These are two of the main sources of hazardous chemical wastes . The US Environmental Protection Agency developed a waste management hierarchy, which states that the most preferred approach is source reduction and reuse, followed by recycling, energy recovery, treatment and disposal. Therefore, the development of a water-based manufacturing technique which limits the amount of hazardous chemicals at the source is essential to the minimization of chemical wastes. This will lead to higher resource efficiency and more efficient recycling and recovery of processing waste. That is precisely what this proposal will target. The vision is to develop facile, inexpensive, scalable solvent-free lithography for nanomanufacturing, which eliminates solvents in as many lithography processes as possible but doing this in a reliable and functionally enabling manner.

There is a general rule of thumb that the cost of manufacturing doubles every time the precision is improved by a factor of ten. Crudely, this is why it costs billions of pounds to set up a fabrication plant to manufacture microprocessors, where the physical size of the transistors being manufactured is on the length scale of a few nanometre, compared with the cost of setting up a facility to manufacture printed circuit boards which sufficiently cheap to be widely available, but features are on the scale of hundreds of micrometers. There are cases of where this rule can be broken. One is in the use of low-dimensional materials which naturally form on a nanometre length scale. An example of this is graphene, which has received a lot of attention in recent years. It naturally forms in a two-dimensional sheet of carbon atoms, and so does not need to be 'machined' to achieve a nanometre-scale thickness. Such 'bottom-up' processes achieve high resolution at very low cost, which is one reason for the interest. However, they still require electrical contacts to be made to the materials to define a complete device. Ideally, we would like to use only a small quantity of these materials, for example by patterning two metal electrodes separated by only a few nanometre with the low-dimensional material (e.g. graphene) inside the nanogap. As the patterning of the metal one this length scale requires a high resolution process, the cost becomes prohibitive again. This project aims to tackle this manufacturing problem directly by combining an emerging technique called 'adhesion lithography' with the growth of low-dimensional materials to create the structures required to make real electronic devices using these materials. Adhesion lithography uses self-assembled monolayers (SAM) to control how well different materials can stick to each other. This allows one metal to be deposited onto a low-cost substrate, like plastic, and patterned using a low cost, low resolution process and a second to be deposited everywhere over the top. Using the SAM, it is possible to ensure that the second metal does not stick to the first. This allows the second metal to be peeled away from the first, uncovering it in the process and leaving a nanogap all around the edge of the first metal. A nanometre scale structure has therefore been manufactured, but without the associated cost. The peeling process has been shown to be critical to make this work. Therefore, this project aims to design and build a low cost tool to carry out this peeling process on a 10x10 cm length scale, but with a clear route to scaling up to large areas (e.g. an A3 sheet). In addition, we will show that the nanogap can be incorporated with the deposition of a low-dimensional material to create a genuine electronic nanoscale device, but with the cost of a much larger device. We expect the this will allow entirely new devices to be developed for a whole range of applications, from logic to memories to sensors.

Like graphene, a layer of a transition metal dichalcogenide (TMDC), ME2 (where M = transition metal and E = sulfur, selenium or tellurium), consists of a single- or few-atom-thick, covalently bonded lattice. These atomic sheets exhibit extraordinary electronic and optical properties, as they do not suffer from dangling bonds and trap states at the surface. The van der Waals interactions between the layers allows the integration of very different materials without the constraints of crystal lattice matching. Moreover, those few layers can withstand mechanical strains of 10%, which makes these materials particularly suitable for flexible electronic devices, a market expected to be worth more than £10B in the next five years. Heterostructures of 2D materials and graphene have great potential for various electronic, opto-electronic, energy, and sensor applications but are held back by technological limitations. It is the intention of this proposal to take advantage of our recent breakthroughs in electrodeposition of few layer 2D chalcogenides, such as MoS2 and WS2, on metal as well graphene electrodes. We will demonstrate these advantages through a variety of devices which combine state-of-the-art performance together with scalable, industrially acceptable processing on flexible substrates. Working with our project partners we will aim to maximise the potential societal and economic impacts that emerge from this work.

Over the last 40 years, we have seen a transformation in how we use electronic devices in our everyday lives from the emergence of home computing in the 1980s with occasional 'dial-up' connection of a single device in the home to the internet. In contrast, today we have a plethora of smart devices such as televisions, speakers, white goods, central heating and even doorbells all continuously connected to the internet through high speed broadband in addition to our mobile phones, tablets and personal computers. This trend will continue, with smart packaging, ubiquitous environmental monitoring, wearable wellbeing monitors amongst other emerging technologies becoming commonplace. The development of this 'Internet of Things' portents new manufacturing challenges. Silicon-based electronics has developed over this time based on trying to minimise the cost per transistor in electronic components such as microprocessors. In this way, microprocessors can be fabricated with billions of transistors at an affordable cost point. However, it is just not appropriate to use silicon-based electronics for all of these emerging applications because of cost, form factor, environmental and other limitations. Large-area electronics (LAE) is the field which sees the use of new materials and processes to make electronics where the cost per unit area is minimised rather than the cost per device. Displays are perhaps the best known example of LAE, where a layer of electronics sits over an entire screen controlling the light output from each pixel, but other areas are emerging, and in particular the development of basic microprocessors, memories and logic on substrates such as flexible plastics which have radically different form factors from silicon. Also, as the cost of manufacture is much lower than for silicon-based electronics, manufacturing in the UK is a reality. As with silicon, decreasing the physical size of LAE devices leads to performance enhancements, and these will be needed for future generations of smart technologies. but in general the cost of manufacture increases as feature size is reduced, and this makes fabrication at the nanoscale prohibitively expensive. We have been working on a patterning technique called Adhesion Lithography (A-Lith). This allows the reproducible fabrication of gaps ~10 nm in length to be formed between adjacent metal electrodes using only low resolution patterning of the metal electrodes themselves. We have published the design of a tool to do this at https://doi.org/10.17863/CAM.68204 . However, to make an electronic device such as a transistor, we need to put materials into the gap between these metal electrodes. Nanomaterials, such as carbon nanotubes, silicon nanowires, zinc oxide nanowires and graphene, have been shown to have exceptional intrinsic electronic properties as a result of their nanostructure. However, the challenge is usually to put metal electrodes onto these materials to be able to make use of these properties. In this work, we propose to develop the manufacturing processes to bring together A-Lith nanogap manufacture with the bottom-up growth of these nanomaterials so that they naturally grow across the nanogap to make a new generation of electronic devices at low cost. Two such 'nanomaterial-in-nanogap' devices which we will demonstrate are transistors and memristors. The former have been the building block behind traditional electronic circuits. The latter are seen as the building block behind the neuromorphic electronics of the future, where we create electronic devices which take inspiration from the synapses of the brain to operate. This project aims to bring the manufacture of these new nanomaterial-in-nanogap devices for large-area electronics to reality.

Over the past 50 years, society has benefitted from electronic devices getting smaller and smaller. The challenge of making such small devices has meant that the processes have increased dramatically in cost, to the extent that the latest 'printer' of very small features costs up to $100M. Only a small number of high-volume products can sustain such a cost. Nevertheless, new physics can occur, and materials can have novel properties at the smallest scales - the nanoscale. So, for society to use these more widely, we need to develop cheaper ways of making small materials and devices. Otherwise, they are unviable, and research into the opportunities that they provide will be limited. This proposal is about extending a recently developed technique called Displacement Talbot Lithography that uses the interference of light to make very small patterns. We will then combine it with other processes, such as atomic layer deposition that allows materials to be controllably coated with individual layers of atoms, to further decrease the pattern size. The technique is exciting because it combines low-cost with high yield and can be scaled relatively easily to large areas, to further increase manufacturability; important for them to be produced at the scale to be used in society at large. Being a new technique, its potential is still relatively unknown. We will then apply the patterning technique to the manufacture of advanced materials that can combine conventional electronics based on silicon with optical communications. Whilst silicon is a mature material for making electronics, it manages light poorly. By growing crystals of good optical materials such as indium phosphide directly on silicon we will combine the optimum properties of both materials to make an engineered super-material. But this can only be done cost-effectively by using the very fine patterning that is possible with Displacement Talbot Lithography. To achieve these goals, the University of Bath and Cardiff University are combining their expertise and working together. Researchers at Bath are experts in large area nanofabrication whilst those at Cardiff are experts in growing group III-V semiconductor crystals for use in optical communications. We will also be partnering with UK manufacturing industry who have the interest and ability to exploit the results and have the wider industry connections to pass on the benefits up the supply chain: Newport Wafer Fab is an advanced semiconductor processing facility that currently boasts International Rectifier, Motorola, Samsung, STM as its clients, whilst PragmatIC Semiconductor is a world leader in ultra-low-cost flexible electronics.