The overall objective of the PIn3S project is to realize Pilot Integration of 3nm Semiconductor technology. This covers Process Integration, creation of Lithography Equipment, EUV Mask Repair Equipment and Metrology tools capable to deal with 3D structures, defects analysis, overlay and feature size evaluation. Each of these objectives will be achieved by cooperation between key European equipment developers like; ASML, Zeiss, Thermo Fisher, Applied Materials, Nova, KTI involved with their suppliers, involvement of a strong knowledge network based on Universities of Germany, Heidelberg University Hospital, and the Netherland, TU Delft and the University of Twente, complemented with key Technology Institutes such as imec and Fraunhofer. The project addresses Section 15 “Electronics Components & Systems Process Technology, Equipment, Materials and Manufacturing”, Major Challenge 4 “Maintaining world leadership in Semiconductor Equipment, Materials and Manufacturing solutions” and Major Challenge 1 “Developing advanced logic and memory technology for nanoscale integration and application-driven performance” of the ECSEL JU Annual Work Plan 2018. As set out in the Multi Annual Strategic Plan 2018, PIn3S addresses the ambition for the European Equipment & Manufacturing industry for advanced semiconductor technologies to lead the world in miniaturization by supplying new equipment and materials approximately two years ahead of introduction of volume production of advanced semiconductor manufacturers. With the results of the Pin3S project the consortium builds on realizing IC manufacturers to migrate to the 3nm Technology node which enables a class of new products which have more functionality, more performance and are more power efficient. As such it will form the bases for innovations yet to come enabling solutions that address the societal challenges in communication, mobility, health care, security, energy and safety & security.

In line with industry needs, Moore’s law, scaling in ITRS 2013, and ECSEL JU MASP 2017, the main objective of the TAPES3 project is to discover, develop and demonstrate lithographic, metrology, EUV mask technology, devices and process modules enabling 3nm node technology. This is planned with available EUV/NA 0.33 scanners, and with system design and integration of a new hyper NA EUV lithography tool to enable more single exposure patterning at 3nm to create complex integrated circuits. Process steps for 3D devices as alternative to the conventional FINFet will be explored for application in the 3nm node. The impact of the application of these so called 3D devices on circuit topology and logic design will be explored. During the development, specific challenges in metrology for the characterization of 3D devices will be assessed and metrology tools will be newly developed. The result will be demonstrated in the imec pilot line. The TAPES3 project relates to the ECSEL work program topic Equipment, Material and Manufacturing. It addresses and targets, as set out in MASP, the grand Challange of "More Moore Equipment and Materials for sub 10nm technologies" by exploring the requirements and solutions for the 3nm node. The project touches the core of the continuation of Moore’s law. Moreover, the cost aware development process will support the involved companies, and will place them in a preferred position over their worldwide competition. Through their worldwide affiliations, the impact of the TAPES3 project will be felt outside Europe in America and Asia Pacific semiconductor centers and is expected to benefit the European economy a lot by supporting its semiconductor equipment and metrology sectors with innovations, exports and employment.

In the ID2PPAC project the technology solutions for the 2nm node identified in the preceding project IT2 will be consolidated and integrated with the objective to demonstrate that Performance Power Area and Cost (PPAC) requirements for this generation of leading edge logic technology can be achieved. To continue the Moore’s law trajectory to the 2nm node, while meeting PPAC requirements, the combination of further advancements in EUV lithography & masks, 3D device structures, materials and metrology is required. The strength of the project pivots on the focused engagement of leading expert partners in these key interlocking areas and a shared pilot line. The ID2PPAC project, is expected to enable IC-fabs to do EUV-based, single-print, High Volume Manufacturing for the 2nm node by 2025. This technology evolution is driven by the growing demand for compute power which increases more than exponentially with time and has made the world migrate from 1 billion interconnected devices in the “PC era” to 10 billion in the “Mobile + cloud era” to the future “Intelligence era” in which there will be over 100 billion intelligent connected devices. To enable this growth, the semiconductor industry is continuously pursuing technology innovations to realize this progress as has been predicted by Moore’s Law and will continue to do so. The project will also help to expand Europe's technological capacity to act in this field, which is crucial for digitization, (edge) AI and for solving national, European and global societal challenges and will strengthen the consortium of leading European companies and institutes active in this sector.

The 14AMI project is about creating technological solutions for the 14 Angstrom CMOS technology node, including a fully integrated functional CFET (Complementary Field Effect Transistor) as new active CMOS device, and state-of-the-art holistic metrology techniques for both wafer and mask inspection and review. All is aimed to keep the pace in the industry to follow “Moore’s law”. The project addresses the following 3 main pillars that are relevant in enabling manufacture of 14A technology, 1) lithography, 2) metrology and 3) process module integration. In lithography the aim is to realize solutions for the 0.55NA EUV scanner platform to secure 14Angstrom node compliance in performance, that is, resolution, alignment, throughput and optics lifetime. In Metrology the objective is to cover wafer and mask metrology and quality control. The aim is to develop holistic metrology, tools & methods and data analytics to improve overlay, CD and focus measurement and quality control with a Precision to Tolerance, P/T, ratio between 0.1 and 0.3. In process module integration work covers the realization and demonstration of a CFET – Complementary Field Effect Transistor - CMOS device. Three options will be investigated for integration; a monolithic, sequential and a hybrid solution. In addition, the partners will develop a PFAS-free photo resist to reduce the ecological footprint of photolithography processes, and a smart AI based sensor technology to improve vacuum chambers' efficiency and reduce waste. At societal level the expected impact of the 14AMI project will support the partners and their supplier network to stay at the leading edge of high-tech developments, crucial to meet the digitization challenges of the European society. Moreover, 14AMI will “boost industrial competitiveness”, and attract talent in Europe, while enabling new application in areas such as security, communication and enabling of further automation in mobility, health and research.

The objective of the 10Ce pThe objective of the 10Ce project is to explore and realize solutions for the 10 CMOS chip technology. Its consortium covers the entire value chain for manufacturing of the CMOS chips in the 10A node, that is, from chip design to lithography to process technology and finally chip metrology. Essential parts of hardware, software and processing technology are developed pushing the boundaries of semiconductor design and manufacture to enable the new node and keep Moores law alive. The 10Ce project is built based on the following four pillars. Lithography Equipment: ASML and expert EUV partners Zeiss, FastMicro, IOM, Plasma Matters, TNO, TU/e, University of Twente and VDL-ETG will: Increase key performance indicators of the EUV tool, to enable smaller pitches and increase yield. Increase sustainability of the EUV tool, both during production as well as increasing the times a module in an EUV tool can be refurbished. Chip design and mask optimization: Imec with the involvement of expert imaging , CAD and IP design partners ARM, ASML and Siemens will: Assess the impact of the introduction of 3D mCFET on chip design: in terms of power, performance and area. Development of new computational lithography solutions to print 10 CFET structures, to improve imaging by next generation mask design. Process Technology: As the ultimate device for logic, the CFET architecture is proposed and Imec and expert partners Coventor, EVG, IBS, Intel, JSR, LAM, RECIF, TEL, Zeiss and Wooptix will: Demonstrate a fully functional monolithic CFET (mCFET) Increase sustainability of the chip manufacturing process, across the manufacturing process and including resist material development. Process characterization: Applied Materials and expert partners Thermofisher, Nova, KLA and Bruker will: Explore and realize high throughput and sample density per wafer, for the analysis, characterization for 10 3D CFET devices, interconnect and materials