Within the food chain of equipment delivery for the semiconductor industry, Europe has kept a very strong position in the metrology area with many companies establishing themselves as main leaders in the field. Hence in line with the objectives of the ICT25 call for innovation action to overcome the (initial) barriers for the successful commercialization of novel European products, this project aims at exploring for a number of metrology solutions their technological readiness, reliability and relevance of the developed protocols, and the COO. The portfolio within the project covers new metrology concepts addressing specifically the processing challenges linked to 3D-Devices and range from probing basic layer properties (composition, electrical properties) in FEOL to control of metallization in BEOL up to issues linked to die stacking. Due to the specific processing steps which need to be addressed, three separate metrology tools will be assessed in this project i.e a Tofsims system (IonTOF) with build-in Scanning Probe stage and FIB column for true 3D-composition profiling, a completely automated micro-Hall and sheet resistance measurement tool (Capres) with additional capabilities for measurements on dedicated test structures (prior to full BEOL) and an GHz acoustic Microscope (Tepla) for probing voids in TSV’s and stacked dies. As some of them (IonTOf, Capres) are addressing partly complementary information (composition versus electrical properties), their co-existence in this project creates additional value as beyond the tool assessment also a methodology based on combining these concepts can be explored and certified. Moreover a significant efficiency gain is created as they can employ similar test structures and devices. For each of these tools, the basic metrology concepts are existing and validated in the lab on selected applications but their general applicability field within the semiconductor industry still needs to be established

In the ID2PPAC project the technology solutions for the 2nm node identified in the preceding project IT2 will be consolidated and integrated with the objective to demonstrate that Performance Power Area and Cost (PPAC) requirements for this generation of leading edge logic technology can be achieved. To continue the Moore’s law trajectory to the 2nm node, while meeting PPAC requirements, the combination of further advancements in EUV lithography & masks, 3D device structures, materials and metrology is required. The strength of the project pivots on the focused engagement of leading expert partners in these key interlocking areas and a shared pilot line. The ID2PPAC project, is expected to enable IC-fabs to do EUV-based, single-print, High Volume Manufacturing for the 2nm node by 2025. This technology evolution is driven by the growing demand for compute power which increases more than exponentially with time and has made the world migrate from 1 billion interconnected devices in the “PC era” to 10 billion in the “Mobile + cloud era” to the future “Intelligence era” in which there will be over 100 billion intelligent connected devices. To enable this growth, the semiconductor industry is continuously pursuing technology innovations to realize this progress as has been predicted by Moore’s Law and will continue to do so. The project will also help to expand Europe's technological capacity to act in this field, which is crucial for digitization, (edge) AI and for solving national, European and global societal challenges and will strengthen the consortium of leading European companies and institutes active in this sector.