The last decade has seen a significant shift in the way computers are designed. Up to the turn of the millennium advances in performance were achieved by making a single processor, which could execute a single program at a time, go faster, usually by increasing the frequency of its clock signal. But shortly after the turn of the millennium it became clear that this approach was running into a brick wall - the faster clock meant the processor got hotter, and the amount of heat that can be dissipated in a silicon chip before it fails is limited; that limit was approaching rapidly! Quite suddenly several high-profile projects were cancelled and the industry found a new approach to higher performance. Instead of making one processor go ever faster, the number of processor cores could be increased. Multi-core processors had arrived: first dual core, then quad-core, and so on. As microchip manufacturing capability continues to increase the number of transistors that can be integrated on a single chip, the number of cores continues to rise, and now multi-core is giving way to many-core systems - processors with 10s of cores, running 10s of programs at the same time. This all seems fine at the hardware level - more transistors means more cores - but this change from one to many programs running at the same time has caused many difficulties for the programmers who develop applications for these new systems. Writing a program that runs on a single core is much better understood than writing a program that is actually 10s of programs running at the same time, interacting with each other in complex and hard-to-predict ways. To make life for the programmer even harder, with many-core systems it is often best not to make all the cores identical; instead, heterogeneous many-core systems offer the promise of much higher efficiency with specialised cores handling specialised parts of the overall program, but this is even harder for the programmer to manage. The Programme of projects we plan to undertake will bring the most advanced techniques in computer science to bear on this complex problem, focussing particularly on how we can optimise the hardware and software configurations together to address the important application domain of 3D scene understanding. This will enable a future smart phone fitted with a camera to scan a scene and not only to store the picture it sees, but also to understand that the scene includes a house, a tree, and a moving car. In the course of addressing this application we expect to learn a lot about optimising many-core systems that will have wider applicability too, and the prospect of making future electronic products more efficient, more capable, and more useful.

The worldwide software market, estimated at $250 billion per annum, faces a disruptive challenge unprecedented since its inception: for performance and energy reasons, parallelism and heterogeneity now pervade every layer of the computing systems infrastructure, from the internals of commodity processors (manycore), through small scale systems (GPGPUs and other accelerators) and on to globally distributed systems (web, cloud). This pervasive parallelism renders the hierarchies, interfaces and methodologies of the sequential era unviable. Heterogeneous parallel hardware requires new methods of compilation for new programming languages supported by new system development strategies. Parallel systems, from nano to global, create difficult new challenges for modelling, simulation, testing and verification. This poses a set of urgent interconnected problems of enormous significance, impacting and disrupting all research and industrial sectors which rely upon computing technology. Our CDT will generate a stream of more than 50 experts, prepared to address these challenges by taking up key roles in academic and industrial research and development labs, working to shape the future of the industry. The research resources and industrial connections available to our CDT make us uniquely well placed within the UK to deliver on these aspirations. The "pervasive parallelism challenge" is to undertake the fundamental research and design required to transform methods and practice across all levels of the ICT infrastructure, in order to exploit these new technological opportunities. Doing so will allow us to raise the management of heterogeneous concurrency and parallelism from a niche activity in the care of experts, to a regularised component of the mainstream. This requires a steady flow of highly educated, highly skilled practitioners, with the ability to relate to opportunities at every level and to communicate effectively with specialists in related areas. These highly skilled graduates must not only have deep expertise in their own specialisms, but crucially, an awareness of relationships to the surrounding computational system. The need for fundamental work on heterogeneous parallelism is globally recognised by diverse interest groups. In the USA, reports undertaken by the Computing Community Consortium and the National Research Council recognise the paradigm shift needed for this technology to be incorporated into research and industry alike. Both these reports were used as fundamental arguments in initiating the call for proposals by the National Science Foundation (NSF) on Exploiting Parallelism and Scalability, in the context of the NSF's Advanced Computing Infrastructure: Vision and Strategic Plan which calls for fundamental research to answer the question of "how to enable the computational systems that will support emerging applications without the benefit of near-perfect performance scaling from hardware improvements." Similarly, the European Union has identified the need for new models of parallelism as part of its Digital Agenda. Under the agenda goals of Cloud Computing and Software and Services, parallelism plays a crucial role and the Commission asserts the need for a deeper understanding and new models of parallel computation that will enable future technology. Given the UK's global leadership status it is imperative that similar questions be posed and answered here.

We propose a Centre for Doctoral Training in Integrative Sensing and Measurement that addresses the unmet UK need for specialist training in innovative sensing and measurement systems identified by EPSRC priorities the TSB and EPOSS . The proposed CDT will benefit from the strategic, targeted investment of >£20M by the partners in enhancing sensing and measurement research capability and by alignment with the complementary, industry-focused Innovation Centre in Sensor and Imaging Systems (CENSIS). This investment provides both the breadth and depth required to provide high quality cohort-based training in sensing across the sciences, medicine and engineering and into the myriad of sensing applications, whilst ensuring PhD supervision by well-resourced internationally leading academics with a passion for sensor science and technology. The synergistic partnership of GU and UoE with their active sensors-related research collaborations with over 160 companies provides a unique research excellence and capability to provide a dynamic and innovative research programme in sensing and measurement to fuel the development pipeline from initial concept to industrial exploitation.