As the communication bandwidth and the bandwidth density scale with Moore’s law, the reach-capability of copper links shrinks, while the optical solutions at very high data rates (enhanced by Wavelength Division Multiplexing -WDM-) are costly and power greedy. 850nm Vertical Cavity Surface Emitting Laser (VCSEL) links dominate at distances from 1 to a few 100 meters, where they provide a significant cost and power benefit, but this solution does not scale with the interconnect needs of mass market applications, such as high performance computer applications and data center applications. The PICSEL project focuses on the development of a new Silicon-Photonics hybrid III/V-on-Si-laser source. The PICSEL source is a long-wavelength (1.5µm to 1.3µm) Vertical Cavity Laser, where bottom and top mirrors are replaced by silicon Photonic Crystal grating-Mirrors (PCM), 1-making the cavity shorter, 2-enabling precise frequency laser emission according to accurately-controlled wavelengths through the lithographic definition of the filling factor of the crystal grating-mirror, and, 3-allowing edge-coupling of the light into a waveguide. With the proposed source, called VCSEEL for “Vertical Cavity Surface and Edge Emitting Laser”, the PICSEL project addresses fabrication cost, bandwidth density (high capacity, high integration density) and power efficiency issues: - Fabrication cost: the PICSEL laser source will be developed in cost-effective mass-scale CMOS front-end fabrication lines; - High capacity: the VCSEEL source is expected to be faster than conventional VCSELs thanks to shorter cavity lengths, thus it has the potentiality to be modulated at higher bitrates; it also offers scalability of the bandwidth density, thanks to its capability to “edge-emit” light into a silicon waveguide, thus enabling WDM-multiplexing of VCSEEL-array into a single waveguide; - High integration density: the aforementioned WDM capability of edge-emission of VCSEELs enables higher integration density, as several (n>4) channels using several VCSEEL lasers can be designed and fabricated on a same chipset, when using an integrated multiplexer (such as AWG), nx10Gbps or nx25Gbps chip-sets will considerably increase the integration density thus substantially decrease the equipment footprint. - Power efficiency: sub milli-amperes threshold current and 20% wall-plug efficiency typical for VCSEL source, are expected. This novel technology paves the way for a new generation of VCSEL devices which should result in a fully successful replacement of the present VCSEL photonics, by employing existing CMOS processing capability, allowing for a high-throughput mass fabrication. Also, the complete renewal of physical concepts will result in the broadening of accessible functionality and application spectra and grants solid perspectives of a promising industrial potential, whose far-reaching future developments can hardly be appreciated in full as today. This later upstream aspect will be addressed in PICSEL and a specific functionality will be demonstrated: the free-space beam steering of arrays of VCSEELs. With a complementary and vertically-integrated consortium covering the whole food-chain, including design, fabrication, and test and with CMOS-compatible front-end processes and III-V-fab available back-end processes, the project PICSEL paves the way for a 3-year-term industrial solution. In addition, “upstream” concepts, enabled by the proposed laser architecture, will be investigated as they are expected to offer enhanced transmission and processing performances.

The main objective of this project is to demonstrate the feasibility of cold cathodes for emitting electrons in vacuum with high current density (> 0,1 A/cm2). This type of cathode would allow almost immediate start-up of the device ( delay time 3.1019 cm-3 ). We propose to deposit this layer by « Atomic Layer Epitaxy » (ALE). The project is organised as research cycles following the fabrication and characterization sequence of the final cathode demonstrators. One cycle includes : (1) Study and fabrication by MOCVD epitaxy, at 3-5 lab, of P+ doped GaN epitaxial layers on single crystal sapphire, SiC or GaN, with maximum electrical conductivity. (2) Study and realization, at LMI, by ALE process, of very thin (< 30 nm) ZnO layers , N++ doped, onto P+ doped GaN. (3) Optimization of the fabrication process of cathode chips at 3-5 lab, chip processing and related on-wafer characterization. (4) Mounting of Cathode chips onto metallic base plates, under the responsibility of 3-5 lab. (5) Physical characterization at ILM of the electron beam emitted by the cathodes under high vacuum. The final project demonstrators will be cathodes mounted on metallic base plates with their emitted electron beam characterized under vacuum ( current density, perveance, electron energy spectrum ).