SiPearl was spun off from the European Processor Initiative (EPI) with €7.4m of initial funding to develop high-end microprocessors and protect European chip sovereignty. In the past 2 years, SiPearl has partnered and contracted with Arm and other top-tier IP providers, secured a €4.6M order book and identified a €1.1Bn sales pipeline in Europe alone. SiPearl is currently raising an €80M+ Series A. We are confident to close this round by year-end based on the achievements of the past 3 months: lead term sheet from a lead corporate investor of our industry, 25M€ venture loan from the EIB, €15M follow-on grant from EPI and additional LOIs from several corporate and public investors. We are currently hiring 7-10 employees per month in Europe. This funding application relates to an additional €2.5M EIC grant + €15M EIC equity which is meant to support the development of our next generation HELIOS platform architecture that supports the new European Chips Act by reducing the cost and time of new chip designs.”

This project proposes to design OpenCUBE, a full-stack solution of a validated European Cloud computing blueprint to be deployed on European hardware infrastructure. OpenCUBE will develop a custom cloud installation with the guarantee that an entirely European solution like SiPearl processors and Semidynamics RISC-V accelerators can be deployed reproducibly. OpenCUBE will be built on industry-standard open APIs using Open Source components and will provide a unified software stack that captures the different best practices and open source tooling on the operating system, middleware, and system management level. It will thus provide a solid basis for the European cloud services, research, and commercial deployments envisioned to be core for federated digital services via Gaia-X. To remain competitive for the European Green Deal, OpenCUBE is designed to make energy awareness a core feature at all levels of the stack, exploiting the advanced features of the SiPearl Rhea processor family at the hardware level and exposing the necessary API at the site level, up to and including interfaces to the electricity grid. This project will leverage representative workloads like those of ECMWF characteristics for production and Digital Twin workflows as drivers for the design and deployment of the cluster infrastructure. We will collaborate closely with the projects developing the virtual environments and the open hardware interfaces for current and future European processor and coprocessor technology.

Building on top of outcomes from the EPI and EUPilot projects, RISER will develop the first all-European RISC-V cloud server infrastructure, significantly enhancing Europe's open strategic autonomy. RISER will leverage and validate open hardware high-speed interfaces combined with a fully-featured operating system environment and runtime system, enabling the integration of low-power components, including the RISC-V processor chips from EPI and EUPilot and LPDDR4 memories, in a novel energy-efficient cloud architecture. RISER brings together a set of 7 partners from industry and academia to jointly develop and validate open-source designs for standardized form-factor system platforms suitable for supporting cloud services. Specifically, RISER will build the following two cloud infrastructures: (1) An accelerator platform, which includes the ARM-based RHEA processor from EPI and a PCIe acceleration board that will be developed within the project which will integrate up-to four RISC-V based EPI and EUPilot chips. (2) A microserver platform, which interconnects up to ten microserver boards all developed by the project, each one supporting up to four RISC-V chips coupled with high-speed storage and networking. Embracing hyperconvergence, the microserver architecture will allow for distributed storage and memory to be used by any processor in the system with very low overhead. The open-source system board designs of RISER will also be accompanied by open-source low-level firmware and systems software, and a representative Linux-based software stack to support cloud services. To evaluate and demonstrate the capabilities of the RISER platforms we will develop three use cases: (a) Acceleration of compute workloads, (b) Networked object and key-value storage, and (c) Containerized execution as part of a provider-managed IaaS environment. RISER will offer open access to the microserver platform, facilitating uptake and enhancing the commercialization path of project results.

The Mont-Blanc 2020 (MB2020) project ambitions to initiate the development of a future low-power European processor for Exascale. MB2020 lays the foundation for a European consortium aiming at delivering a processor with great energy efficiency for HPC and server workloads. A first generation product is scheduled in the 2020 time frame. Our target is to reach exascale-level power efficiency (50 Gflops/Watt at processor level) with a second generation planned for 2022. Therefore, we will, within MB2020: 1. define a low-power System-on-Chip (SoC) implementation targeting Exascale, with built-in security and reliability features; 2. introduce strong innovations to improve efficiency with real-life applications and to outperform competition (vector instruction implementation, memory latency and bandwidth, power management, 2.5D integration); 3. develop key modules (IPs) needed for this implementation; 4. provide a working prototype demonstrating MB2020 key components and system level simulations, with a co-design approach based on real-life applications; 5. explore the reuse of these building blocks to serve other markets than HPC. Our key choices are: a) To use the ARM ISA (Instruction Set Architecture) because its has strong technological relevance and it offers a dynamic ecosystem, which is needed to deliver the system software and applications mandatory for successful market acceptance. b) To design, implement or leverage new technologies (Scalable Vector Extension, NoC, High Bandwidth Memory, Power Management, …) as well as innovative packaging technologies to improve the versatility, performance, power efficiency, reliability, and security of the processor. c) To improve on the economic sustainability of processor development through a modular design that allows to retarget our SoC for different markets.

Several European flagship projects have emerged towards European sovereignty in chip design and computing infrastructure. Among them, the EU Processor Initiative (EPI) spearheads the development of the first EU processor. To ensure the successful integration of the EU processor into the cloud computing ecosystem and strengthen even more EU data sovereignty, it is necessary to develop the software support at the same pace with the hardware development. The harmonic relationship of the developed software and hardware is of paramount importance in order to establish an EU cloud platform able to compete with the mainstream solutions which are currently delivered by US companies. AERO aims to upbring and optimize an open-source software ecosystem that encompasses a wide range of software components ranging from operating systems to compilers, runtimes, system software and auxiliary software deployment services for cloud computing. The AERO software stack combines the aforementioned software components with novel software and hardware interfaces as a means to seamlessly exploit the heterogeneity aspects of the EU processor with regards to high performance, energy efficiency, and security. The ultimate objective of AERO is to facilitate easy migration of existing cloud customers to a cloud infrastructure that harnesses the capabilities of the EU processor. To showcase early adoption and the potential business value, the developed software and hardware technologies will be piloted by use cases representative of important EU industrial domains, such as automotive and space exploration.