The provision of future services in the digital economy is reliant on achieving more power efficient computers. Recent bandwidth improvements in electronic interconnects have only been achieved at the expense of dramatic increases in latency and power consumption [19]. Photonic technologies appear essential to make chip-to-chip communication sustainable for ever-higher data rates due to inherently lower power operation. Recent advances in silicon photonics, photonic printed circuit boards (PCB) and 3D integration technologies indicate great promise for short distance photonics. However, given the radical changes in computer design brought about by chip multiprocessors (CMP) and the fundamental differences between electronic and photonic communications, the design implications for complete computer systems are not clear. The proposed research will study the implications of upcoming photonic technologies on the power consumption and architecture of large computer systems such as high performance computers and data centres. The uniqueness of the proposal is its method and the holistic results that it should produce. I will start with a firm scientific foundation based on characterisation of emerging photonic devices leading to models of existing and predicted future components. FPGA-based emulation will enable investigation of complete multi-chip, multi-core computer systems and interconnect running at around 1/100th of real time. The outcome will be the knowledge to build large computer systems optimised for minimum power consumption. This multidisciplinary research therefore underpins several EPSRC themes: digital economy, next-generation healthcare and energy efficiency as well as responding to the EPSRC signposted Moore-for-Less microelectronic grand challenge.

This proposal is concerned with the automatic design of reconfigurable architectures. The proposed approach forms a radical departure from standard industrial and academic practice in reconfigurable architecture design. The main feature of this approach is its basis in formal global optimization proceduresfrom the mathematical programming and operations research communities, in contrast to the empirical approaches typically used to attack this problem.The intention is to develop and extend mathematical models of power consumption, computation throughput, and silicon area usage, and incorporate these within a mathematical programming framework. This will allow the simultaneous optimization of multiple architectural and synthesis parameters, leading to provable-quality solutions, and eliminating the dependence of the resulting architecture on heuristic bias.Promising preliminary results have already been achieved, providing provably optimal bounds on the relative computational speed of various DSP benchmarks compared to ASIC implementations of the same circuits, and proposing architectures resulting in up to 20% speed improvement (for the same area) or 60% area reduction (for the same speed) over commercial architectures.Funding is requested for a post-doctoral research associate (3 years) and a Ph.D. student (3.5 years) to work with the investigators.

We are at a pivotal point in the design of computational devices.Technology scaling favours transistors over wires which has moved usinto an era where communication takes more time and consumes morepower than the computation itself. We believe that this technologydriver inextricably pushes us toward a communication-centric approachto computer system design from both hardware and softwareperspectives. This grant application is focused on exploring this newcommunication-centric view of computer system design from engineeringwires through computer architecture, compiler design, language designand application mapping. It is our wish that this grant form aportfolio of projects tackling future computational systems involvingthousands of power efficient processors.Communication-centric design can be viewed at several levels ofabstraction:Level 0 - implementation technology, where we will focus oncommunication networks-on-chip.Level 1 - computer architecture, focusing on optimisation ofcommunication flows in the system.Level 2 - algorithm mapping to allow automated placement of data andcode across a manycore computing surface.Level 3 - programming language and compiler design to allowparallelism and locality to be easily expressed.An FPGA based simulation infrastructure will also be constructed toallow research results to be obtained from hardware work at levels 0and 1, and to efficiently support software research undertaken atlevels 2 and 3.

The provision of future services in the digital economy is reliant on achieving more power efficient computers. Recent bandwidth improvements in electronic interconnects have only been achieved at the expense of dramatic increases in latency and power consumption [19]. Photonic technologies appear essential to make chip-to-chip communication sustainable for ever-higher data rates due to inherently lower power operation. Recent advances in silicon photonics, photonic printed circuit boards (PCB) and 3D integration technologies indicate great promise for short distance photonics. However, given the radical changes in computer design brought about by chip multiprocessors (CMP) and the fundamental differences between electronic and photonic communications, the design implications for complete computer systems are not clear. The proposed research will study the implications of upcoming photonic technologies on the power consumption and architecture of large computer systems such as high performance computers and data centres. The uniqueness of the proposal is its method and the holistic results that it should produce. I will start with a firm scientific foundation based on characterisation of emerging photonic devices leading to models of existing and predicted future components. FPGA-based emulation will enable investigation of complete multi-chip, multi-core computer systems and interconnect running at around 1/100th of real time. The outcome will be the knowledge to build large computer systems optimised for minimum power consumption. This multidisciplinary research therefore underpins several EPSRC themes: digital economy, next-generation healthcare and energy efficiency as well as responding to the EPSRC signposted Moore-for-Less microelectronic grand challenge.

Optical network infrastructure has underpinned the Internet pervading everyone in some way and has stimulated relentless traffic growth. Current network infrastructure is made of stacked layers of function rigid systems. That includes optical switching nodes in conjunction with a set of transmission (i.e. 100Gbps and beyond) and transport (e.g. OTN) systems as well as Layer 2 switches, IP routers, to deliver end-to-end network infrastructure. Such networks are designed and optimised to deliver a fixed set of functionalities for the lifetime of their deployment. Recently there is a shift towards creating a more flexible control and transport by use of software defined network (SDN). SDN however introduces an inbuilt assumption that there is relatively dumb hardware for data switching and forwarding while having relatively intelligent software. This inherently restricts the flexibility of a network environment. The vision behind this project is to introduce and investigate a radically new and groundbreaking approach to accommodate future infrastructure needs in a more agile, flexible, programmable and evolvable manner down to the hardware level. This will be delivered by open programmable hardware eco-system (photonic and electronic) where the software/hardware programmable devices can be synthesized on-demand to support any and as many function(s) and layers and be re-purposed during their lifetime. Software/Hardware network functions can be interconnected electronically and/or optically to compose and synthesize a system on demand. This is an original and disruptive concept and proposal that defines the Synthetic Node and Network system. It is expected to deliver a breakthrough on Internet and beyond. The synthesis will consist of interconnection of electronic (e.g. FPGA processing blocks) and photonic (e.g. switching, elastic filtering, amplification, multicasting, etc.) function blocks to compose an fused on-chip off-chip system necessary to perform a particular function and deliver the associated network performance. Such approach eliminates the notion of dimensioning, deploying and provisioning applied on traditional networks designed with function rigid systems. The software-hardware function blocks can be also re-used on any future general-purpose programmable hardware (e.g FPGA/SoC) eliminating disruptive migration lifecycles. This also allows for network users (e.g. operators, service providers) to re-purpose the functions on their physical or virtual infrastructure on demand to suit the network service needs. This inherently redefines the system infrastructure and creates a new research field that fuses electronic and photonic programmability that opens up a new set of opportunities and challenges. The project will first investigate the formulation of function block behaviour realised both in electronics (i.e. data queuing, framing, protocols) and photonics (i.e. filtering, multiplexing, frequency/space switching). Such function blocks will be interconnected by an network topology (on-chip and off-chip) through the use of synthesis algorithms to compose a complete system. To deliver efficient synthesis, the composition framework and algorithms will consider infrastructure constraints (FPGA timing/space, and optical sub-system characteristics). Techniques will be devised and investigated to deliver isolation between distinct network programmable functions that co-exist on the same opto-electronic hardware substrate. The project provides direct contribution spanning across multiple EPSRC Priority Areas such as ICT networks and distributed systems as well as optical communications and micro-electronics design. Specifically it addresses the Towards an Intelligent Information Infrastructure (TI3) challenge. So it consequently fits with the EPSRC Working Together priority. It is this context that SONATAS is vital to the development of the future of information society.