Multimedia coding systems today cannot provide seamless quality degradation under degraded system resources. For example, if one watches a video on a portable video player, or is in the middle of a very important phone call, and this is draining the system resources (battery), current systems do not allow for seamless trade-offs in visual (audio) quality vs battery life (computation). Today the user is practically facing the on/off situation of the digital world, while one would strongly opt for an analogue world, where energy or computational resources (complexity) are traded off with multimedia quality (e.g. visual or audible distortion).We propose to fundamentally alter the way conventional multimedia coding algorithms are computed based on a new paradigm that we call Operational Refinement of Computation for Multimedia Coding Systems . The key principle is based on altering the realization of multimedia coding algorithms to enable the new principle of incremental refinement of computation: under a refinement of the multimedia information (e.g. images/video/audio), the algorithm computation refines the previously-computed result thereby leading to incremental computation of the output. The incremental processing or reconstruction of the input/output multimedia signals enables three key advantages in comparison to existing systems. Firstly, complexity-distortion trade-offs can be formulated since every refinement layer improves upon the quality of the output result (reduces distortion) at the cost of additional complexity. Secondly, each refinement input/output layer typically consists of data with limited dynamic-range (e.g. single-bit precision data). Hence, the complexity of the processing tasks can be modelled more accurately in function of the source statistics. Thirdly, each refinement layer can be scheduled in a different part of the implementation architecture and the computation of all layers can be parallelized. This is expected to increase the execution speed and hardware utilization significantly.This proposal comes at an excellent time. There has been a flurry of research on novel sampling and capturing devices that merge successive-approximation based analogue-to-digital converters with image sensors at the pixel or sample level. This enables the sample-based, or bitplane-based capturing of the input multimedia data. At the same time, very recent results demonstrated that image displays enabling the incremental refinement of a large number of luminance shades without flicker are possible. This enables the incrementally-produced output to be directly consumed by the display monitor. These novel developments in circuit theory and design seem very promising in solving the capturing and display aspects for systems that process the input data incrementally.In summary, conventional systems provide an all or nothing multimedia representation; the computation cannot be interrupted arbitrarily when resources become unavailable and retrieve a meaningful approximation of the final result. Contrasting the existing paradigm, we propose to investigate, for the first time, a new category of best-effort signal processing and multimedia systems. Applications of this type of systems are in all environments where resources may bescarce or uncertain due to environmental constraints, based on user choice, or, finally, by construction. Examples are:* portable multimedia systems with limited energy resources,* resource-constrained adaptive surveillance or monitoring applications with always on features,* fault tolerant multimedia algorithm and system design, and* progressive pricing schemes and progressive upgrades for quality-upgradeable hardware.

Storage of information on optical disks and within random access memory (RAM) chips is central to both present and future information technology. Future storage devices must have larger capacity, shorter access times, smaller physical size and use low power. Existing optical storage formats (e.g DVD-R/W) are based upon a process of structural change within the coating on the disk. By heating the surface of the disk with focused laser pulses, a chalcogenide alloy is driven between amorphous and crystalline phases. Although the technology is well established, our understanding of the structural phase transition is surprisingly limited. A recent study of Ge2 Sb2 Te5 (GST), the most commonly used material, revealed that the material does not necessarily melt in a conventional sense, and suggested that optical excitation of specific electronic states drives a non-thermal phase transition. Electrically addressed phase-change RAM (PCRAM or Ovonic memory) has the potential to replace existing FLASH-based memory, which faces difficulties in scaling to smaller sizes (higher capacities). In contrast PCRAM scales well and is inherently bistable. PCRAM cells rely on a reversible transition between the amorphous and crystalline phases to 'write' data. The transition is accompanied by a dramatic change in electrical resistance that may be easily read out. When a write pulse is supplied to the amorphous material, threshold switching to a low conductivity state is observed before the structural phase change, or memory switching , occurs. The origin of the threshold switching mechanism remains controversial and the intrinsic timescales for threshold switching have, as far as we are aware, never been measured.We propose to use time-resolved femtosecond optical measurement techniques to investigate the phase transition in GST and other chalcogenide alloys. Using conventional optical pump-probe measurements we will determine which phase the material occupies at different times during the switching process and investigate its dependence upon the duration and wavelength of the exciting optical pulse. We will hence understand whether a tailored optical pulse may induce more efficient writing and erasure of an optical disk. Highly optimized sample materials will be supplied by RWTH-Aachen, Plasmon Data Systems Ltd, and ST Microelectronics. We will examine the response of the alloy to the polarization of the optical pulse. The observation of optically induced birefringence may provide a better understanding of the non-thermal nature of the transition and lead to additional applications in optical communications technology. Stroboscopic time resolved optical measurements will also be performed upon prototype PCRAM cells to understand the dynamics of the threshold and memory switching processes in real devices. The ultrafast laser will be synchronised to fast electrical pulse generators that deliver set and reset pulses to the cell, allowing us to determine the instantaneous electronic state of the chalcogenide alloy during both the threshold and memory switching processes. We will also use a short but intense laser pulse to assist the switching processes. By varying the wavelength of the pulse we will investigate the importance of specific electronic transitions in the non-thermal breaking of bonds. Optically-assisted electronic switching of PCRAM devices has, to our knowledge, not been previously attempted. The measurements will be understood, interpreted and guided by multi-scale modelling. Ab-initio Density Functional Theory (DFT) calculations will be performed to determine the crystallographic strucutre, optical properties and electronic band stucture of the material. Physically realistic macroscopic models for predicting the performance of real device (electrical and optical memories) will be developed by 'bridging the gap' between ab-initio atomic scale modelling and existing phenomenological crystallisation models.

The purpose of this work is to investigate an on-chip network fabric that will enable future reconfigurable computing systems integrating tens or hundreds of processing tiles implementing embedded microprocessors, intellectual property cores, reconfigurable fabrics, dedicated local memories and DSP functionality. The reconfigurable NoC fabric will direct the effective communication and exchange of data among the multiple processing tiles and enable fault-tolerance and very high communication bandwidths with low-latency and low energy consumption. The processing tiles will morph their functionality and operation point based on the application demands.

Describe the proposed research in simple terms in a way that could be publicised to a general audience [up to 4000 chars]. Note that this summary will be automatically published on EPSRC's website in the event that a grant is awarded. The recently developed memory architectures based on resistive-variable devices such as Phase Charge Memories, Programmable Metallization Cell or memristors have reliability issues that are drastically different from those affecting CMOS based memories. These novel memories although based on different technologies, they all share the principle of storing information as the resistance value imposed to a resistive-variable devices and consequently also the possible type of faults that may occur. This project proposes to leverage data obtained from experimental results to characterize resistive-variable devices and to exploit both information and architectural redundancies to enhance reliability and yield of these devices. To face the presence of a massive number of defects suitable spare resources, such as spare row and/or columns will be used combined with suitable error detection methods and efficient readdressing scheme to substitute faulty elements. To leverage the use of spares resources, codes novel models and algorithms to estimate the reliability versus overhead trade-off will be developed, with the aim of obtaining a reliability-aware driven synthesis tool for these memory devices.

The purpose of this work is to investigate an on-chip network fabric that will enable future reconfigurable computing systems integrating tens or hundreds of processing tiles implementing embedded microprocessors, intellectual property cores, reconfigurable fabrics, dedicated local memories and DSP functionality. The reconfigurable NoC fabric will direct the effective communication and exchange of data among the multiple processing tiles and enable fault-tolerance and very high communication bandwidths with low-latency and low energy consumption. The processing tiles will morph their functionality and operation point based on the application demands.