Compound Semiconductor (CS) materials are a Key Enabling Technology at the heart of modern society. They are central to the development of, for example, the 5G network, new energy efficient lighting, smart phones, satellite communications systems, power electronics for the next generation of electric vehicles and new imaging techniques. Simply put, these technologies support our connected world, our health, our security and the environment. The next generation of these technologies can only be achieved with a step change in CS manufacturing and we aim to the UK at the centre of this CS manufacturing research. This is not only important activity in its own right but will also support systems researchers in all of these important fields. The step change will be achieved by applying the manufacturing disciplines and approaches of Silicon to Compound Semiconductors and by combining CS with Silicon. This includes developing integrated epitaxial growth and processing with critical yield and reliability analysis; establishing new standards for CS device production, with a guaranteed number of wafer starts per week for key statistical based process control and development via IT infrastructure; solving the scientific and manufacturing challenges in wafer size scale-up combining large scale, 150-200mm diameter growth and fabrication for GaAs based and GaN based materials and apply this to existing and developed advanced processes; introducing a multi-project wafer culture (as is the norm in the silicon world) to share costs and encourage the widespread use of larger wafers by academics and SMEs. Critical to this approach is the characterisation equipment, which can be used in-line (during the manufacturing process) and over the larger (up to 200mm diameter) CS wafers we will utilise. This proposal is for this characterisation equipment to add to the large investment already made by Cardiff University and partners in epitaxial growth and fabrication infrastructure and equipment. We also ask for apparatus to allow high quality insulating layers to be deposited, which will enable the multi-project wafer approach to produce world leading performance, for access by our UK based circuit and system designers.

This first grant project will develop an MBE-LEEM system, combining in-situ state-of-the-art Molecular Beam Epitaxy and a Low Energy Electron Microscope. The project will increase capabilities in sample exchange between institutions, enabling the analysis of nucleation on complex samples, increase reproducibility and accuracy of flux measurements, increase reproducibility and accuracy of temperature control, increase the number of material sources, enabling the growth of new materials, increase safety, reduce down-time of the system and increase control during surface preparation. The development of the MBE-LEEM will enable close collaboration between Cardiff University and EPSRC National Centre for III-V Technologies and with IQE, a world leading semiconductor wafer company. The system will be used for basic research, providing a wealth of data on nucleation dynamics and key epitaxial processes for theorists across UK, and providing industrial and academic partners with a unique characterization technique to determine optimum growth parameters in complex epitaxial processes by analysing growth dynamics. The extended capabilities of the MBE-LEEM will be tested by studying the nucleation of MnAs on InAs, determining the conditions for nucleation of Zinc-Blende MnAs. The nucleation of half-metallic MnAs on an InAs buffer layer with thickness below 2 monolayers was shown by Kim et al. in 2006, but the process has not been reproduced and no explanation on the mechanism leading to Zinc-Blende MnAs has been provided. MBE-LEEM will produce videos of the nucleation of MnAs on InAs with different thicknesses, highlighting the evolution of MnAs crystal structure and morphology during nucleation. The fabrication of half-metallic semiconductors can be key for the development of spintronics. Follow-up research is projected after this first grant development project in order to analyse magnetic properties of half-metallic MnAs, and to apply MBE-LEEM to other key research on epitaxial processes, such as the integration of GaAs on Silicon, or the nucleation of nanostructures.

The past few decades have witnessed an explosive growth in the semiconductor material and device technologies and their profound impact in the shaping of modern society. After experiencing the booming development of personal computer (PC) technology in the 1990s and the upsurge of the Internet in the 2000s, we are embracing a new age of the Internet of Things. As the explosive growth of Internet Protocol (IP) traffic is driving data centres to the so-called "Zettabyte Era", today's electrical interconnects quickly became the bottleneck due to ohmic loss and RC delays of copper wires. Optical interconnects promise to break the bottleneck by enabling data in computers moving both across chips and from chip to chip through photons. Photons are electromagnetic waves with very high frequencies. They can travel at the speed of light and they are super-efficient information carriers. The realisation of optical interconnects requires all optical components from passive to active devices to be integrated on the same silicon-on-insulator platform. Despite great success in developing silicon-based light modulation and detection, the lack of an efficient light emitter due to the indirect bandgap properties of silicon continues to pose a major roadblock. In contrast to silicon, most of III-V compound semiconductors have a direct bandgap with excellent photon absorption and emission efficiency. It is widely perceived that integrating III-V semiconductors, the best available materials for light emitters, on silicon could unpin the transition from electrical to optical interconnects. Epitaxial growth of III-V materials in the desired areas on silicon offers a scalable, low-cost and high-throughput scheme to bring optical capabilities to silicon integrated circuits. However, there are several fundamental challenges associated with material incompatibility, including a large mismatch in the lattice constants and thermal expansion coefficients, and the growth of polar materials on non-polar substrates. Conventional III-V/Si epitaxy circumvents these challenges through multiple buffer layers on bulk silicon wafers. However, thick buffers limit process throughput and present a big barrier for efficient light coupling to the underlying silicon waveguides. In this project, an advanced epitaxy process will be developed to enable an III-V on insulator (XOI) structure integrated on silicon wafers. By taking advantage of the crystallographic geography and selective area growth in confined spaces, we aim to achieve dislocation-free micro-sized thin films on insulators without requesting complex buffer designs. Such a buffer-less platform can potentially support intimate integration of III-V compound semiconductors with silicon waveguides and open enormous opportunities in Si photonics. As a proof-of-concept demonstration, micro-disk lasers will be fabricated to validate the optical quality of the III-V structures and highlight its potential for photonics integration.

AlGaN/GaN high electron mobility transistors (HEMT) are a key enabling technology for future power conditioning applications in the low carbon economy, and for high efficiency military and civilian, microwave and RF systems. Although the performance of AlGaN/GaN HEMTs presently reaches RF powers up to 40W/mm, at frequencies exceeding 300 GHz, their long-term reliability, often thermally limited, is still a serious issue, in the UK & Europe, but also in the USA & Japan. Corresponding challenges exist for power conditioning applications. To mitigate the present thermal device challenges, the aim of this proposal is innovation and step change in thermal management of AlGaN/GaN HEMT devices by developing novel substrates, in particular (1) high value substrates that have higher heat extraction capability than high cost SiC substrates commonly used for GaN RF applications, and (2) low cost substrates that have improved heat extraction capability to GaN-on-Si substrates for more cost sensitive power electronics markets. The resulting step-change in improvement in heat spreading will improve reliability, circuit efficiency and ease system constraints of GaN electronics. To enable the optimization of the thermal substrate properties key enabling new thermal analysis technologies will be developed. The UK has roadmaps for employing RF and microwave GaN electronics in defence as well as satellite communication. The key UK industrial players in this field include Selex, MBDA, Astrium & others, all requiring reliable and efficient GaN RF and microwave electronics, which the proposed work will advance and enable via the new heat extracting substrate technologies and improved methods of thermal characterisation, furthermore with opportunities for IQE UK, supporter of this proposal, of being a key component in the supply chain for RF GaN applications. The corresponding roadmap for power electronics requires cost-effective GaN presently on Si substrates power devices with UK based manufacture at NXP, supporter of this project, and International Rectifier (IR) which the outcome of this proposed work can innovate. Further business opportunities will emerge with the substrate development itself, such as via Element-6, at IQE through the developments of III-Nitride epitaxial growth for best heat extraction, or spin-out companies. Dissemination of results and insights from this project will be via publications in internationally leading journals, via conferences, via the UK Nitrides Consortium, i.e., established dissemination routes will be used to transfer knowledge into academia, and directly with the industrial supporters of this project, as well as other companies Bristol and Bath have links to (e.g. Selex, MBDA). The CDTR in Bristol and the III-Nitride group in Bath have both a strong track record in being successful using these dissemination routes, in particular with companies. The field of thermal management of semiconductor devices is an important academic research field, and is especially topical and useful at the current stage of implementation of this genuinely disruptive technology. It not only trains UK workforce for industry, but also it is essential to help maintain the present high level of device physics and engineering in the UK. It provides stimulus for an efficient interaction between universities and industry to maximize benefit of EPSRC research investment. This includes in this project interaction with UK industry, in particular, IQE, NXP, and Plessey in this project.

To help combat climate change, the UK has a target to reduce carbon emissions by 80% by 2050. This is an enormous task requiring changes to energy generation and supply. To limit the impact on scarce natural resources and the environment, these reductions need to be delivered by providing affordable green energy. The proposed programme will address this very target by developing high-efficiency and low-cost solar cells by growing III-V compound semiconductor self-organised structures on cheap and plentiful silicon. This proposal directly contributes to development of new solar materials and devices to enable the UK to lead in this priority area. The widespread implementation of photovoltaics (PV) [the conversion of sunlight into voltage and therefore power] and solar cells as one means of reaching sustainable energy production for the planet will require vast areas of semiconductor materials to be structured into PV cells in order to capture the power of sunlight. There are two general approaches taken: either to use very large area, low-cost and low-efficiency semiconductor materials (such as organic materials) or to use small-area highly-efficient but expensive semiconductor materials and concentrate the light into the small-area, Concentrator Photovoltaics (CPV). The cost of the housing is a significant cost of the PV cell and therefore making the material cheaper for the large area PV does not improve cost below a certain value. The efficiency of the CPV cells is being improved continuously by improved design, growth and fabrication. Experimentally III-V compound semiconductor CPV cells have recently achieved efficiencies of >40% making them the highest efficiency PV available in any technology. Further increase of efficiency for CPVs is the key for utilizing solar energy worldwide. There are two main design approaches to inorganic III-V semiconductor CPV solar cells: Multi-jumction SCs (MJSCs) and intermediate band solar cells (IBSCs). In MJSCs a number of semiconductor material junctions are connected in-series, each designed to efficiently absorb a section of the solar spectrum appropriate to its bandgap with the largest bandgap material placed at the front and the smallest bandgap material placed at the back. A single junction SC has a maximum predicted efficiency of 30% while a double-junction comprised of two optimised bandgaps increases the predicted efficiency to 41%. Much effort has gone into designing a number of MJSCs with an increased number of junctions. Intense effort is going into investigating materials to absorb near the peak of the spectrum around 1.0 eV. We propose to use 1.0-eV bandgap Quantum Dots (QDs) as a solution for this. A QD is one semiconductor embedded into another and arises from self-organised growth. QDs enable material combinations to be grown together that would not normally occur in a planar environment as strain is incorporated into the interface-this allows novel materials to be combined in a QD system opening up new material combinations and allowing these materials to be grown on silicon using only a thin germanium sandwich layer. In IBSCs an intermediate energy band (IB) is introduced into the energy gap of the single semiconductor material junction introducing three possible optical transitions. The photo-generated carriers in the intermediate level must only link to the host material through optical transitions for the IBSC to function correctly. The IBSC with one IB level is predicted to have ultra-high conversion efficiency up to 63% while increasing the number of IB levels up to 4 is predicted to increase efficiencies up to 80%. However these high efficiencies are not observed experimentally. We will investigate using QD systems to make IBSCs. We will exploit the advantages of both QD technology and germanium-on-silicon substrates to develop the low-cost and high-efficiency III-V/Si solar cells of both MJSC and IBSC design.