14ACMOS is about enabling manufacture of 14A Semiconductor technology. It addresses the 4 key pillars in IC technology development for manufacture; Lithography, Metrology, Mask Infrastructure and Process technology. Carl ZEISS, Trumpf and ASML are the main parties to push the lithography solutions to 14A. Between Carl ZEISS, Fraunhofer, RWTH, UW and TNO further understanding of optics life time and plasma physics is pursued in optimizing optics transmission and lifetime. Nova, BRT, ILT and PTB address measurement sensitivity enhancement of X-ray and optical based methodologies to meet the 14A requirements. Imec, TNO, PTB, UPB and RWTH will combine and tune metrology techniques specifically for the assessment of EUV reticle degradation. On throughput and resolution enhancement Bruker, EXC, PTB and AMIL will work on X-ray sources and AMIL, ICT and NFI on e-beam and SPM platforms for in-line metrology. On the reduction of Total Measurement Uncertainty, Prodrive and AMIL cover the development of an ultra-high precision wafer stage and NVIDIA, AMIL and Prodrive the development of a next generation image processing system. In Mask Infrastructure there are FHG (IISB), ASML, Carl Zeiss covering the creation of a simulation based mask repair strategy and with Carl ZEISS, ASML, PI and UPB HW/SW and process technology for particle removal is created and repair durability is covered with Carl ZEISS, ASML, Suss and UPB. Process technology covers the creation of patterning solutions with the involvement of imec and TEL. On active device selection there will be imec, Cadence, IBS, JSR, Recif and TEL with THERMO enabling advanced TEM characterization. Middle Of Line and Back End Of Line solution development is with imec, TEL, Solmates and Coventor for process modules and Cadence the interface with the design community. On Sustainable Semiconductor Technology and Systems there are imec, Recif and ThermoFisher covering sustainable material and processing alternatives.

In the ID2PPAC project the technology solutions for the 2nm node identified in the preceding project IT2 will be consolidated and integrated with the objective to demonstrate that Performance Power Area and Cost (PPAC) requirements for this generation of leading edge logic technology can be achieved. To continue the Moore’s law trajectory to the 2nm node, while meeting PPAC requirements, the combination of further advancements in EUV lithography & masks, 3D device structures, materials and metrology is required. The strength of the project pivots on the focused engagement of leading expert partners in these key interlocking areas and a shared pilot line. The ID2PPAC project, is expected to enable IC-fabs to do EUV-based, single-print, High Volume Manufacturing for the 2nm node by 2025. This technology evolution is driven by the growing demand for compute power which increases more than exponentially with time and has made the world migrate from 1 billion interconnected devices in the “PC era” to 10 billion in the “Mobile + cloud era” to the future “Intelligence era” in which there will be over 100 billion intelligent connected devices. To enable this growth, the semiconductor industry is continuously pursuing technology innovations to realize this progress as has been predicted by Moore’s Law and will continue to do so. The project will also help to expand Europe's technological capacity to act in this field, which is crucial for digitization, (edge) AI and for solving national, European and global societal challenges and will strengthen the consortium of leading European companies and institutes active in this sector.

Listen2Future will boost the potential of piezoelectric acoustic transducers to provide new solutions in the key application areas of Health & Wellbeing and Digital Industry & Energy. Acoustic transducer solutions and the key underlying technologies are addressing many of the challenges in emerging applications towards a more digitalized society. Indeed, growing demand for MEMS-based acoustic transducers (microphones, ultrasonic transducers) in medical and industrial devices are creating a new high demand for miniaturized low power sensors. In combination with an intelligent signal processing system, algorithms and customized packaging, these technologies will be the key to achieve performant, low power consuming, miniaturized and cost-saving systems. The demonstrators will address 14 use-cases in LISTEN2FUTURE with their benchmark in low power consumption, small size and low cost to open the door for disruptive acoustic applications. Major impact on quality of live for humans as well as on industrial and medical appliances can be expected. The European Position in Acoustic Sensors will be therefore strengthened by new piezoelectric materials and technologies with the capability to outperform the existing ones that are based on capacitive MEMS technologies. This will contribute to reinforcing the Union's strategic autonomy in electronic components and systems to support future needs of vertical industries and the economy at large. The growth of the microphone market (8 -> 14bio. units in 5 years) and the growth of the Ultrasound sensing modules market (500mio -> 800mio in 3 years) should be predominantly covered with acoustic sensors made in Europe. The double transition of European Union toward digital and greener society there poses a high demand for reliable and secure data. Our integral acoustic sensor solutions are listening to these needs and mapping the acoustic senses and perceptions into Society 5.0.

The objective of the ACT10 project is to develop and demonstrate the required technology options, including their integration, for the 10Ångstrom node. The 32 participating partners cover a wide range of activities along the entire value chain for the manufacturing of CMOS chips. Activities include equipment development, computer aided design tooling and process technology development. Essential parts of hardware, software and processing technology are developed pushing the boundaries of semiconductor design and manufacture to enable the new node and keep Moore’s law alive. The project aims to enhance the attractiveness of the EU as a location for new cutting-edge high volume and legacy node fabs. The ACT10 project is built based on the following four pillars. 1. Lithography Equipment and Mask Technology: Increase key-performance indicators in the optical system of High-NA Lithography machines, along with developing advanced mask processes and equipment to reach optical imaging requirements, and nonlinear optics material lifetime effects. 2. Chip design and Block Level validation; Assessment of different CFET devices and evaluate building blocks for digital and analog IPs. 3. Process Technology: development of innovative solutions for routing of the stacked n- and p-devices of the CFET architecture, development of 0.55NA (high-NA) single patterning solutions, and the development of semi-damascene BEOL for the 10Å node. 4. Computational Metrology and Process Monitoring Equipment: develop computational metrology methods, and develop metrology and inspection modules and equipment.

The challenges and major HiCONNECTS objectives are to transform the centralized cloud platform to decentralized platforms which include edge cloud computing in a sustainable, energy-efficient way. This will bring cloud services including Artificial Intelligence (AI) closer to the IOT end-users, which enables them to really use the COT and IOT efficiently. The technologies underpinning this revolutionary step include the development of high-performance computing, storage infrastructure, network interfaces and connecting media , and the analysis of IOT sensors and big data in real-time. This major step forward will enable, for example, the mobile clients (during the 5G deployment phase and 6G exploration) to move among different places with minimum cost, short response time and with stable connection between cloud nodes and mobile devices. The main underlying technology to be developed by the HiCONNECTS consortium, comprising large industrial players, universities and RTO’s, and many SMEs, can be summarized under the title: ’heterogenous integration’ (HI) which is needed to meet the computing power, bandwidth, latency and sensing requirements for the next generation cloud and edge computing and applications. The HI revolution brings the electronic components and systems (ECS) into a new domain, which combines traditional silicon wafers integrated circuit (IC), InP based high speed electronics , and Si and InP photonics devices and interconnect. The HiCONNECTS ambition is to demonstrate, through HI development, a leap in computing and networking reliability and performances across the full vertical and horizontal ECS value chain (i.e. essential capabilities and key applications) in a sustainable way. In addition, HiCONNECTS will focus on the development of next generation design, algorithms, equipment (HW/SW), systems and Systems of Systems (SOS).