The SFINCS project (Semi-Formal INstrumentation for Circuits and Systems) investigates and develops new technologies for SoC validation. SFINCS addresses Assertion-Based Verification (ABV). During the design process, assertions (written for instance in PSL or in SVA) help describe:  the results expected from the device (assert). These assert statements can be checked through the design flow using observation monitors.  the constraints on the inputs (assume). Input sequences satisfying these assume statements can be produced by test sequence generators. The aim of this project (see Figure 1) is to develop and integrate methodologies to apply ABV to a variety of hardware systems, using a uniform approach founded on a technology conceived in the TIMA Laboratory. We target the following designs:  synchronous IPs described at the RT level  pseudo-synchronous, mixed functions and GALS systems (Globally Asynchronous Locally Synchronous)  HW/SW system aspects described at the SystemC TLM (transactional) level  application to complex, mixed SoC and to safety critical systems. In the HORUS prototype tool developed by the TIMA laboratory, synthesizable designs are automatically produced in Verilog or in VHDL for:  synchronous or asynchronous observation monitors  test sequence generators  interfaces and history tracing mechanisms. The approach is based on a library (VHDL or Verilog) of primitive components, one for each PSL or SVA primitive operator, and an interconnection scheme, both of them formally proven correct. It leads to optimised and synthesizable VHDL or Verilog descriptions. Through the cooperation between the TIMA Laboratory and the Dolphin and Thales Communications companies, we will mainly carry out the following tasks:  implementation by Dolphin of the HORUS technology for building synchronous monitors and test generators in the mixed signal simulation environment. Its incorporated tool for power consumption estimation will be useful for evaluating the consumption induced by the assertion logic. The HORUS method will be advantageous from early simulation to FPGA prototyping.  the complete development of the emerging technique for building asynchronous monitors, and its implementation in the environment of Dolphin. This approach covers a wide range of applications domains (GALS, mixed functions, critical systems,...). Testbenches will be provided by Thales Communications. In particular, the technology will be experimented on safety critical components for avionics or security.  the extension to descriptions of complex SoCs written in SystemC at the TLM (transactional level modelling) level. TIMA is currently defining an object-oriented model for adapting the monitoring approach of HORUS to this level. The technique will be fully specified, and implemented as a prototype tool. Its applicability to realistic designs will be demonstrated by experiments on SoC testbenches selected by Thales Communications.

Computers are used in a variety of space-borne equipment for numerous on-board applications and processors are at the core of these equipment. However, currently existing space-grade processors are not suitable to be used in the next generation spacecraft computing platforms because they do not provide sufficient performance, power-efficiency and are too expensive. On the other hand, ARM processors are known to be extremely power-efficient and low-cost while providing high performance and are at the core of the vast majority of terrestrial application markets such as smart phones, tablet computers, and other embedded devices. Future space processors and current terrestrial are now converging, as for safety and mission critical market segments there is a growing concern about radiation effects even at the ground level. Therefore TCLS ARM FOR SPACE targets the following high level objectives: - Bring one of the mainstream CPUs with the largest software eco-system into the space sector (ARM Cortex R5) - Establish an innovative radiation hardened methodology for this CPU making it attractive to both space and terrestrial applications - Study the portability to European latest and highest performance hardened semiconductor technology (STM65nm) This is achieved by the collaboration of the most experienced companies in this field, namely Airbus Defence and Space (G, F) for specific heritage on high reliable and radiation hardened systems, ARM (UK) providing its excellence in processor core IPs and know-how in this field of developments and Atmel (F) and Dolphin (F) contributing with their space and STM65nm technology experience and knowledge respectively. This activity will allow the incorporation of research groups (ARM Research Group) and SMEs (Dolphin) into the space landscape. The exploitation and the dissemination of the results will be guaranteed by the wide sales and marketing network provided by Airbus DS and Atmel for the space and ARM for the terrestrial sectors.

High speed imaging is a booming activity with the ideal application of CMOS technology imagers. It makes it possible to acquire a fast single event at a fast sampling and frame rate and to observe it at a reduced frame rate. It finds many applications in motion analysis, explosives, ballistic, biomechanics research, crash test, airbag deployment, manufacturing, production line monitoring, deformation, droplet formation, fluid dynamics, particle, spray, shock & vibration, etc. High speed video imaging is currently driven by some industrial manufacturers such as Photron, Redlake, Drs Hadland, which design their own sensors. The current industrial most efficient imagers offer a speed of 22,000 frames per second (fps) for a spatial resolution of 1280x800 pixels, i.e. 22 Gpixel/s. This speed is not restricted by the electronics of the pixel but by the sensors chip inputs/outputs interconnections. The conventional operation mode based on extracting the sensor data at each acquisition of a new image is a real technological barrier that limits the scope of high speed cameras to the study of transient phenomena that last for a few hundred microseconds. The FALCON project's main goal is to overcome this technological barrier, increasing the acquisition speed by three orders of magnitude by proposing a sensor capable of taking up to 100 million fps while increasing the sampling rate up to 10 TeraPixel/s. To accomplish this, the classical approach of extracting image sensor should be abandoned in favor of a new one which makes it possible to eradicate the inputs/outputs bottleneck. Several studies mention the realization of high-speed image sensors based on the principle of "burst" imagers (BIS Burst Image Sensor). Since it is impossible to get the frames out of the sensor as they are acquired, the idea is to store all the images in the sensor and execute the readout afterward, after the end of the event to be recorded. So far, all the developed BIS based on this principle use a totally analog approach in the form of a monolithic sensor. The size of the embedded memory is generally limited to a hundred frames, the pixel pitch is around 50 µm and the acquisition rate is in the order of 10 Mfps for large 2D arrays. Furthermore, research works mention little data about the signal to noise ratio (SNR), but the leakage current of the storage capacities degrades the signal quality and the effect is more noticeable when the readout duration is high, i.e. when the number of stored images is large. This phenomenon limits, once again, the number of storable images in analog BIS forms. In general, a maximal SNR of 45 dB is obtained. The FALCON project is based on a device concept in total disruption with previous works, by implementing the possibilities offered by the emergent microelectronics 3D technologies in order to increase the performance of this type of sensor while also adding more features to it. A PhD work started in 2012 in collaboration between the CEA Leti and the ICube laboratory helped to determine an optimal sensor architecture that takes advantage of the 3D technology. A particularity of the proposed architecture is the in-line analog to digital conversion at full speed. This study shows that the proposed new approach increases the number of stored images, while increasing the signal to noise ratio. It has also brought light to the potential problems of heat dissipation inherent to both fast circuits and 3D technologies. The methodological aspects of the design are also at the center of the project seeing that architecture/partitioning and electronic/thermal co-designs are necessary to carry out this type of conception. New tools and methods for the design of integrated heterogeneous systems are needed. The ultimate objective of the project is a high definition 1200x1200 pixels, 10 Mega fps with more than 1000 frames embedded digital memory. The project is pushing the performances of all the system bricks to the state of the art.