Abstracts are not currently available in GtR for all funded research. This is normally because the abstract was not required at the time of proposal submission, but may be because it included sensitive information such as personal details.

Moore's law states that, since their invention in 1947, every two years the number of transistors on an integrated circuit doubles. This is due to the shrinking of devices through advances in technology. However, as these devices are approaching the atomistic level, intrinsic variations are becoming more abundant, leading to a lower production yield and higher failure rates. In order to accommodate the increased variability of individual device characteristics there is a need for novel device architectures and circuit design methodologies. For example, Intel were forced to make the biggest change in transistor technology since the 1960s in order to reach the 45nm CMOS technology node. These predictions and issues were originally focussed on large-scale integration, mainly connected with microprocessor design. However, in the last 10 years the rise of Field Programmable devices (e.g. Field Programmable Gate Arrays - FPGA) both in terms of technology advances and application domains has meant that these issues are now relevant to these devices as well. Hence, the proposal focuses upon one of the current greatest challenges in electronic design: taking physical effects of intrinsic variability into account when the shrinking of device sizes approaches atomistic levels, in order to achieve functional circuit designs. Both process and substrate variations impose major challenges on the reliable fabrication of such small devices. These variations fall into two categories; deterministic variability, which can be accurately modelled and accounted for using specific design techniques, and stochastic variability, which can only be modelled statistically and is harder to overcome. The proposal will develop a reconfigurable design platform that can be manipulated at the device and digital abstraction levels in order to further understand and tackle the effects of stochastic variability in hardware upon next generation designs.The research proposal comprises four threads that build upon each other:- Design of a simulation model for a variability tolerant architecture, - Hardware realisation of this model,- Development of a comprehensive software framework, which will be able to interface the simulation model as well as the chip,- Development of bio-inspired approaches to tackle variability tolerant design. At its conclusion the project will have developed an understanding of how stochastic variability will affect circuit design in the future and will propose novel design methodologies to overcome stochastic variability. A novel, variability tolerant architecture will have been developed and realised as a simulation model and as a prototype in hardware. Both are vital steps towards next generation FPGA architectures.

Abstracts are not currently available in GtR for all funded research. This is normally because the abstract was not required at the time of proposal submission, but may be because it included sensitive information such as personal details.

Largely driven by material scientists, the flexible electronic research thus far has focussed on the materials and fabrication techniques. Whilst these are important areas, device modelling and circuit design is critical for taking the research closer to manufacturing. The acceptable degree of bendability for reliable operation of devices and circuits is a question that has not been addressed so far. This is a challenging because the standard transistor models for circuit simulation programs such as SPICE do not take into account the dynamic bendability induced effects. FLEXELDEMO will address these challenges by systematically characterizing the ultra-thin chips, identifying various parameters that change with bending, and suggesting improved BSIM models for devices over bendable substrates. This project has several anticipated benefits over a range of time-scales. In the short-term, this project will substantially improve our understanding of changes in various device parameters as a result of bending (uni-axial, bi-axial or twisting etc.), which has traditionally been under-studied. In the medium-term, it will enable designing of electronics on bendable substrate and predicting the behaviour of bendable electronics just like we do currently for planar electronics. In the long-term, the project will lead to intelligent use of bendability in improving circuit design. For example, location or shape dependent strain-field variations will be used to design location-/shape-aware circuits or to compensate electronic artefacts (e.g. self-calibration). The approach could also lead to design on bendable electronics based on ensemble of nanowires. Formulating the design rules and integration strategies through modelling will help in stabilizing the nascent flexible electronics technology. By adequately supporting the fabrication activities with modelling and simulation, this project will add significant new perspective to the fields of flexible electronics and electronics design.

Among the physical limitations which challenge progress in nanoelectronics for aggressively scaled More Moore, process variability is getting ever more critical. Effects from various sources of process variations, both systematic and stochastic, influence each other and lead to variations of the electrical, thermal and mechanical behavior of devices, interconnects and circuits. Correlations are of key importance because they drastically affect the percentage of products which meet the specifications. Whereas the comprehensive experimental investigation of these effects is largely impossible, modelling and simulation (TCAD) offers the unique possibility to predefine process variations and trace their effects on subsequent process steps and on devices and circuits fabricated, just by changing the corresponding input data. This important requirement for and capability of simulation is among others highlighted in the International Technology Roadmap for Semiconductors ITRS. SUPERAID7 will build upon the successful FP7 project SUPERTHEME which focused on advanced More-than-Moore devices, and will establish a software system for the simulation of the impact of systematic and statistical process variations on advanced More Moore devices and circuits down to the 7 nm node and below, including especially interconnects. This will need improved physical models and extended compact models. Device architectures addressed in the benchmarks include especially TriGate/ΩGate FETs and stacked nanowires, including alternative channel materials. The software developed will be benchmarked utilizing background and sideground experiments of the partner CEA. Main channels for exploitation will be software commercialization via the partner GSS and support of device architecture activities at CEA. Furthermore, an Industrial Advisory Board initially consisting of GLOBALFOUNDRIES and STMicroelectronics will contribute to the specifications and will get early access to the project results.