The TAKE5 project is the next in a chain of thematically connected ENIAC JU KET pilot line projects which are associated with 450mm/300mm development for the 10nm technology node and the ECSEL JU project SeNaTe aiming at the 7nm technology node. The main objective of the TAKE5 project is the demonstration of 5nm patterning in line with the industry needs and the ITRS roadmap in the Advanced Patterning Center at the imec pilot line using innovative design and technology co-optimization, layout and device architecture exploration, and comprising demonstration of a lithographic platform for EUV technology, advanced process and holistic metrology platforms and new materials. A lithography scanner will be developed based on EUV technology to achieve the 5nm module patterning specification. Metrology platforms need to be qualified for 5nm patterning of 1D, 2D and 3D geometries with the appropriate precision and accuracy. For the 5nm technology modules new materials will need to be introduced. Introduction of these new materials brings challenges for all involved deposition processes and the related equipment set. Next to new deposition processes also the interaction of the involved materials with subsequent etch steps will be studied. The project will be dedicated to find the best options for patterning. The project relates to the ECSEL work program topic Process technologies – More Moore. It addresses and targets as set out in the MASP at the discovery of new Semiconductor Process, Equipment and Materials solutions for advanced CMOS processes that enable the nano-structuring of electronic devices with 5nm resolution in high-volume manufacturing and fast prototyping. The project touches the core of the continuation of Moore’s law which has celebrated its 50th anniversary and covers all aspects of 5nm patterning development.

The objective of the 3DAM project is to develop a new generation of metrology and characterization tools and methodologies enabling the development of the next semiconductor technology nodes. As nano-electronics technology is moving beyond the boundaries of (strained) silicon in planar or finFETs, new 3D device architectures and new materials bring major metrology and characterization challenges which cannot be met by pushing the present techniques to their limits. 3DAM will be a path-finding project which supports and complements several existing and future ECSEL pilot-line projects and is linked to the MASP area 7.1 (subsection More Moore). Innovative demonstrators and methodologies will be built and evaluated within the themes of metrology and characterization of 3D device architectures and new materials, across the full IC manufacturing cycle from Front to Back-End-Of-Line. 3D structural metrology and defect analysis techniques will be developed and correlated to address challenges around 3D CD, strain and crystal defects at the nm scale. 3D compositional analysis and electrical properties will be investigated with special attention to interfaces, alloys and 2D materials. The project will develop new workflows combining different technologies for more reliable and faster results; fit for use in future semiconductor processes. The consortium includes major European semiconductor equipment companies in the area of metrology and characterization. The link to future needs of the industry, as well as critical evaluation of concepts and demonstrators, is ensured by the participation of IMEC and LETI. The project will directly increase the competitiveness of the strong Europe-based semiconductor Equipment industry. Closely connected European IC manufacturers will benefit by accelerated R&D and process ramp-up. The project will generate technologies essential for future semiconductor processes and for the applications enabled by the new technology nodes.

14ACMOS is about enabling manufacture of 14A Semiconductor technology. It addresses the 4 key pillars in IC technology development for manufacture; Lithography, Metrology, Mask Infrastructure and Process technology. Carl ZEISS, Trumpf and ASML are the main parties to push the lithography solutions to 14A. Between Carl ZEISS, Fraunhofer, RWTH, UW and TNO further understanding of optics life time and plasma physics is pursued in optimizing optics transmission and lifetime. Nova, BRT, ILT and PTB address measurement sensitivity enhancement of X-ray and optical based methodologies to meet the 14A requirements. Imec, TNO, PTB, UPB and RWTH will combine and tune metrology techniques specifically for the assessment of EUV reticle degradation. On throughput and resolution enhancement Bruker, EXC, PTB and AMIL will work on X-ray sources and AMIL, ICT and NFI on e-beam and SPM platforms for in-line metrology. On the reduction of Total Measurement Uncertainty, Prodrive and AMIL cover the development of an ultra-high precision wafer stage and NVIDIA, AMIL and Prodrive the development of a next generation image processing system. In Mask Infrastructure there are FHG (IISB), ASML, Carl Zeiss covering the creation of a simulation based mask repair strategy and with Carl ZEISS, ASML, PI and UPB HW/SW and process technology for particle removal is created and repair durability is covered with Carl ZEISS, ASML, Suss and UPB. Process technology covers the creation of patterning solutions with the involvement of imec and TEL. On active device selection there will be imec, Cadence, IBS, JSR, Recif and TEL with THERMO enabling advanced TEM characterization. Middle Of Line and Back End Of Line solution development is with imec, TEL, Solmates and Coventor for process modules and Cadence the interface with the design community. On Sustainable Semiconductor Technology and Systems there are imec, Recif and ThermoFisher covering sustainable material and processing alternatives.

In line with industry needs, Moore’s law, scaling in ITRS 2013/2015, and ECSEL JU MASP 2016, the main objective of the TAKEMI5 project is to discover, develop and demonstrate lithographic, metrology, process and integration technologies enabling module integration for the 5 nm node. This is planned with available EUV/NA0.33 scanners that are optimized for mix and match with existing DUV/NA1.35 scanners, and with system design and development of a new hyper NA EUV lithography tool to enable more single exposure patterning at 5 nm to create complex integrated circuits. Process steps for modules in Front-end, Middle and Back-end of line are discovered and developed using the most advanced tool capabilities and they are evaluated morphologically and electrically using a relaxed test vehicle. During the development, specific challenges in metrology are assessed and metrology tools are upgraded or newly developed. The results are demonstrated in the imec pilot line with qualified metrology tools at the 5 nm node. The TAKEMI5 project relates to the ECSEL work program topic Process technologies – More Moore. It addresses and targets, as set out in the MASP, at a (disruptive) new Semiconductor Process, Equipment and Materials solutions for advanced CMOS processes that enable the module integration of electronic devices for the 5nm node in high-volume manufacturing and fast prototyping. The project touches the core of the continuation of Moore’s law which has celebrated its 50th anniversary. The cost aware development process supports the involved companies, and places them in an enhanced position for their worldwide competition. Through their worldwide affiliations, the impact of the TAKEMI5 project will be felt outside Europe in America and Asia Pacific semiconductor centers and is expected to benefit the European economy a lot by supporting its semiconductor equipment and metrology sectors with innovations, exports and employment.