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26 Projects, page 1 of 6
  • Funder: French National Research Agency (ANR) Project Code: ANR-07-NANO-0022
    Funder Contribution: 676,739 EUR
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  • Funder: European Commission Project Code: 325633
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  • Funder: European Commission Project Code: 826422
    Overall Budget: 119,166,000 EURFunder Contribution: 26,752,400 EUR

    The overall objective of the PIn3S project is to realize Pilot Integration of 3nm Semiconductor technology. This covers Process Integration, creation of Lithography Equipment, EUV Mask Repair Equipment and Metrology tools capable to deal with 3D structures, defects analysis, overlay and feature size evaluation. Each of these objectives will be achieved by cooperation between key European equipment developers like; ASML, Zeiss, Thermo Fisher, Applied Materials, Nova, KTI involved with their suppliers, involvement of a strong knowledge network based on Universities of Germany, Heidelberg University Hospital, and the Netherland, TU Delft and the University of Twente, complemented with key Technology Institutes such as imec and Fraunhofer. The project addresses Section 15 “Electronics Components & Systems Process Technology, Equipment, Materials and Manufacturing”, Major Challenge 4 “Maintaining world leadership in Semiconductor Equipment, Materials and Manufacturing solutions” and Major Challenge 1 “Developing advanced logic and memory technology for nanoscale integration and application-driven performance” of the ECSEL JU Annual Work Plan 2018. As set out in the Multi Annual Strategic Plan 2018, PIn3S addresses the ambition for the European Equipment & Manufacturing industry for advanced semiconductor technologies to lead the world in miniaturization by supplying new equipment and materials approximately two years ahead of introduction of volume production of advanced semiconductor manufacturers. With the results of the Pin3S project the consortium builds on realizing IC manufacturers to migrate to the 3nm Technology node which enables a class of new products which have more functionality, more performance and are more power efficient. As such it will form the bases for innovations yet to come enabling solutions that address the societal challenges in communication, mobility, health care, security, energy and safety & security.

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  • Funder: French National Research Agency (ANR) Project Code: ANR-17-CE05-0019
    Funder Contribution: 595,488 EUR

    The evolution of energy requirements due to increased electrical applications and consumption but also to the diversification of technologies linked to the renewable energy development lead to modify transport, distribution and energy management methods (i.e smart-grids, HVDC,…). In this context, the emergence of power devices suitable for harsh environments (e.g. high-voltage, high-frequency, high temperature, radiated environments, …) is expected to address transforming the current electric grid to the future grid. For example, power converter technologies have to be adapted and semiconductor switches have to comply with breakdown voltages well above 10 kV. The wide band gap (WBG) semiconductors, with theirs electronic and electrothermal properties, allow fabricating power devices operating at high voltage, high frequency and high temperature. Over recent years, several innovative wide bandgap power devices have been proposed and commercialized, the most known are SiC power MOSFET (Wolfspeed) and GaN HEMT (EPC, GaN System). The interest of these semiconductor materials is to overcome the “specific on-resistance/breakdown voltage” trade-off limit of silicon conventional power devices In such a context, Diamond is a good candidate to address several of the aforementioned issues. Its electrical properties (bandgap, thermal conductivity, charge-carrier mobility, critical electric field) are undoubtedly the highest among other semiconductors. However, Diamond is the technologically least mature semiconductor. The ambitious aim of the MOVeToDiam project is to create breakthrough by developing crucial Diamond technological steps to design and fabricate the next generation of power devices operating at 300°C as a vertical p-channel MOSFET U gate (Diam-UpMOSFET), and a very high voltage diamond TMBS diode (Trench MOS Barrier Schottky). Demonstration of the feasibility of these Diamond devices, requires basic research with high potential for disruptive technologies such as n and p-type diamond layers stacking, low resistive ohmic contacts on both diamond types, diamond/dielectric interface states control and vertical trench gate etching. Such challenges can be raised thanks to the international and complementary expertise in the development of technological bricks, specific to the diamond field of 4 academic laboratories, namely LSPM, GEMaC, AMPERE as well as LAAS, and the IBS Company. This p-channel vertical power MOSFET based on single crystal diamond and TMBS diode will allow France to be the forerunner and achieve low size, low weight, integrated and efficient power modules operating at high frequencies. These systems will be used on green transports and smart energy grid, major fields of interest in sustainable development. These researches would enable France to be the leader in the Diamond technology applied to very high voltage fields.

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  • Funder: French National Research Agency (ANR) Project Code: ANR-23-ASM2-0010
    Funder Contribution: 507,650 EUR

    The civilian market for SiC power devices has been driven by an exponential growth since the 2010s, thanks to the needs of automotive and solar industry. The industrial offer is now mature for 1200 V and 1700 V SiC components, either diodes, MOSFETs. However, the higher the breakdown voltage goes, the sparser the market offer gets. This results from lesser market size, and technological difficulties that remain to be solved. However, SiC semiconductor is probably even more attractive for higher voltages range (3.3kV-10kV) when compared to Si solutions. It is worth noticing that at higher breakdown voltage class bipolar transistors such as GTOs are expected to be available earlier than MOSFETs because of their higher current and voltage capabilities, and the more complex reliability issues for the latter transistor. So bipolar devices will be relevant for the civilian market, even if they are deemed less convenient application-wise. One of the most straightforward application of high voltage SiC thyristor is pulsed power electronics. In this sense, Institut Saint Louis (ISL) and Ampère laboratory have been studying extensively the potential of the SiC technology to design and build efficient thyristors able to cope with high voltage and high peak current capabilities. These studies allowed creating a large quantity of knowledge and knowhow almost unique in the field, at least in Europe. The CARTHAGE project presents an opportunity to transform the previously developed concepts by ISL+Ampère in a semi-industrial product using stable, repetitive and in-line controlled processing. Based on these observations, the Carthage partners jointly believe that it is now feasible to develop, prototypes and test advanced SiC thyristors, and once packaged demonstrate their performances and potential for civilian and military applications (reaching then TRL 5). The CARTHAGE project aim to provide such a demonstration. Also, the number of wafers to be processed has been chosen to provide first estimates of yield as well as, hopefully, a final number of functional devices commensurate with future demonstrations of system applications, especially for military use cases. In this sense, the project integrates different objectives and related activities which will cover the product’s value chain. The first objective is to transfer the SiC thyristor fabrication technology in a semi-industrial processing platform, with the objective to mature and stabilize the fabrication process and allow the production of reasonable number of reliable chips (>200) per batches. For this purpose, it is important to study and improve the integration of large area devices while limiting the stacking faults degradation. Another target is to adapt and optimize the design of the thyristor architecture, including the high voltage edge termination, to the novel technology platform. A task to optimize an assembly and packaging technology adapted to high-pulsed current density and high power density operation is also required and a main target of the project. The last objective will be to demonstrate the full value chain from material to characterization in an application subsystem. To reach these goals, a consortium including a combination of complementary academic and industrial partners (CEA-Leti, ISL, Ampère, IBS, DEEP Concept) has been built in order to cover the value chain from starting semiconductor material to the component characterization in a subsystem. The complementarity of the partner will not only allow to reach the technical objectives but also to bring new insights in the physics and general understanding of SiC processing technology. In addition, the partners have a long collaboration background on SiC and power devices in general, which will allow a good understanding and efficiency in the scientific and technical interactions.

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