Up to now two kinds of graphene membranes for gas filtration applications have been made: very selective membrane by adding graphene oxide on porous material or membrane with an excellent permeance due to the atomic thickness of CVD grown graphene decorated with nanometer size pore holes. GATES project aims at making the laboratory demonstration at a TRL level 4 of a new membrane made of CVD graphene that will be both highly selective (103) between H2 (He) and CO2, N2, O2, Ar gases and with a high permeance (10-5 mol m-2 s-1 Pa-1 ). The project concept lies on technological innovations on the device and pore holes realization. The developed processes will be compatible with a CMOS technology to insure manufacturability. The device fabrication will escape one of the roadblock of graphene technology, which is its transfer step after the growth of the Single Layer Graphene (SLG). This step is hard to industrialize, and induces many macroscopic defects that can degrade largely the yield of membrane production. The ambition of GATES is to develop and demonstrate a technology without transfer, CMOS compatible. Ultimately, two devices will be stacked to increases the selectivity by adding tortuosity. To achieve a very high selectivity, it is mandatory to have sub nanometer pore diameter. In GATES, initial pyridinic-N or pyrrolic-N vacancies on the SLG will be created by nitrogen doping using different plasma technologies. If needed, these vacancies will be further etched. An alternative approach, to be evaluated in GATES, is to make nano-pores by using heavy ions produced at GANIL (Grand Accélérateur National d'Ions Lourds) facility. In both cases, the shapes and pores size statistics will be evaluated by advanced TEM observations performed in the consortium. These statistics will be used as input parameters for the modelling of the membrane performances. Furthermore, other complementary characterization techniques, as Raman spectrometry and X-ray photoelectron spectroscopy (XPS), will be employed for having deep knowledge of the produced membranes. In the project the filtering properties of undoped, N-doped and functionalized nano-porous graphene will be modelled. Ultimately, double-layered functionalized graphene will be also modelled. This modelling work will support the experimental developments and will be used to define the optimum structure for the best permeability/selectivity ratio. GATES will also assess the porosity due to grain boundaries by simulating different local environments, e.g. pentagons-heptagons. The development of such a graphene membrane and its application to leak detection, will offer a significant innovative product for users by providing a highly portable/integrated device with a very short response time.

The WAKEMEUP project objective is to set-up a pilot line for advanced microcontrollers with embedded non-volatile memory, design and manufacturing for the prototyping of innovative applications for the smart mobility and smart society domains. The already defined microcontrollers with 40nm embedded flash technology will be consolidated to build a solid manufacturing platform. Additional developments will be performed for the integration of memory, power management, connectivity, hard security on the same chip. The project will also target the industrialization of the embedded Phase Change Memory (PCM) technology built on top of the FDSOI 28nm logic process pilot line. The development of the ePCM will be driven by the final application requirements as well as decreasing the power consumption. The alternative memory solutions will be also studied as they have different - and complementary - traits in such areas as read/write speed, power and energy consumption, retention and endurance, and device density and benchmarked with the ePCM and the conventional eFlash. Continued advances in materials, device physics, architectures and design could further reduce the energy consumption of these memories. To achieve this goal of generating high value added semiconductor circuits in Europe in a breakthrough leading edge technology the project will deploy all the necessary activities to bring a new technology to an early industrial maturity stage. These activities encompass such developments as: technology enhancements for various specific application requirements such as wide temperature range and reliability, high security requests, high flexibility…, design enablment allowing first time silicon success, prototyping demonstrator products in the different application areas. In the WAKEMEUP project, new devices and systems will be developed by the application partners in automotive and secure based on FD-SOI and embedded digital technology to answer specific applications needs.

The overall objective of the PIn3S project is to realize Pilot Integration of 3nm Semiconductor technology. This covers Process Integration, creation of Lithography Equipment, EUV Mask Repair Equipment and Metrology tools capable to deal with 3D structures, defects analysis, overlay and feature size evaluation. Each of these objectives will be achieved by cooperation between key European equipment developers like; ASML, Zeiss, Thermo Fisher, Applied Materials, Nova, KTI involved with their suppliers, involvement of a strong knowledge network based on Universities of Germany, Heidelberg University Hospital, and the Netherland, TU Delft and the University of Twente, complemented with key Technology Institutes such as imec and Fraunhofer. The project addresses Section 15 “Electronics Components & Systems Process Technology, Equipment, Materials and Manufacturing”, Major Challenge 4 “Maintaining world leadership in Semiconductor Equipment, Materials and Manufacturing solutions” and Major Challenge 1 “Developing advanced logic and memory technology for nanoscale integration and application-driven performance” of the ECSEL JU Annual Work Plan 2018. As set out in the Multi Annual Strategic Plan 2018, PIn3S addresses the ambition for the European Equipment & Manufacturing industry for advanced semiconductor technologies to lead the world in miniaturization by supplying new equipment and materials approximately two years ahead of introduction of volume production of advanced semiconductor manufacturers. With the results of the Pin3S project the consortium builds on realizing IC manufacturers to migrate to the 3nm Technology node which enables a class of new products which have more functionality, more performance and are more power efficient. As such it will form the bases for innovations yet to come enabling solutions that address the societal challenges in communication, mobility, health care, security, energy and safety & security.

In line with industry needs, Moore’s law, scaling in ITRS 2013/2015, and ECSEL JU MASP 2016, the main objective of the TAKEMI5 project is to discover, develop and demonstrate lithographic, metrology, process and integration technologies enabling module integration for the 5 nm node. This is planned with available EUV/NA0.33 scanners that are optimized for mix and match with existing DUV/NA1.35 scanners, and with system design and development of a new hyper NA EUV lithography tool to enable more single exposure patterning at 5 nm to create complex integrated circuits. Process steps for modules in Front-end, Middle and Back-end of line are discovered and developed using the most advanced tool capabilities and they are evaluated morphologically and electrically using a relaxed test vehicle. During the development, specific challenges in metrology are assessed and metrology tools are upgraded or newly developed. The results are demonstrated in the imec pilot line with qualified metrology tools at the 5 nm node. The TAKEMI5 project relates to the ECSEL work program topic Process technologies – More Moore. It addresses and targets, as set out in the MASP, at a (disruptive) new Semiconductor Process, Equipment and Materials solutions for advanced CMOS processes that enable the module integration of electronic devices for the 5nm node in high-volume manufacturing and fast prototyping. The project touches the core of the continuation of Moore’s law which has celebrated its 50th anniversary. The cost aware development process supports the involved companies, and places them in an enhanced position for their worldwide competition. Through their worldwide affiliations, the impact of the TAKEMI5 project will be felt outside Europe in America and Asia Pacific semiconductor centers and is expected to benefit the European economy a lot by supporting its semiconductor equipment and metrology sectors with innovations, exports and employment.

The 14AMI project is about creating technological solutions for the 14 Angstrom CMOS technology node, including a fully integrated functional CFET (Complementary Field Effect Transistor) as new active CMOS device, and state-of-the-art holistic metrology techniques for both wafer and mask inspection and review. All is aimed to keep the pace in the industry to follow “Moore’s law”. The project addresses the following 3 main pillars that are relevant in enabling manufacture of 14A technology, 1) lithography, 2) metrology and 3) process module integration. In lithography the aim is to realize solutions for the 0.55NA EUV scanner platform to secure 14Angstrom node compliance in performance, that is, resolution, alignment, throughput and optics lifetime. In Metrology the objective is to cover wafer and mask metrology and quality control. The aim is to develop holistic metrology, tools & methods and data analytics to improve overlay, CD and focus measurement and quality control with a Precision to Tolerance, P/T, ratio between 0.1 and 0.3. In process module integration work covers the realization and demonstration of a CFET – Complementary Field Effect Transistor - CMOS device. Three options will be investigated for integration; a monolithic, sequential and a hybrid solution. In addition, the partners will develop a PFAS-free photo resist to reduce the ecological footprint of photolithography processes, and a smart AI based sensor technology to improve vacuum chambers' efficiency and reduce waste. At societal level the expected impact of the 14AMI project will support the partners and their supplier network to stay at the leading edge of high-tech developments, crucial to meet the digitization challenges of the European society. Moreover, 14AMI will “boost industrial competitiveness”, and attract talent in Europe, while enabling new application in areas such as security, communication and enabling of further automation in mobility, health and research.