14ACMOS is about enabling manufacture of 14A Semiconductor technology. It addresses the 4 key pillars in IC technology development for manufacture; Lithography, Metrology, Mask Infrastructure and Process technology. Carl ZEISS, Trumpf and ASML are the main parties to push the lithography solutions to 14A. Between Carl ZEISS, Fraunhofer, RWTH, UW and TNO further understanding of optics life time and plasma physics is pursued in optimizing optics transmission and lifetime. Nova, BRT, ILT and PTB address measurement sensitivity enhancement of X-ray and optical based methodologies to meet the 14A requirements. Imec, TNO, PTB, UPB and RWTH will combine and tune metrology techniques specifically for the assessment of EUV reticle degradation. On throughput and resolution enhancement Bruker, EXC, PTB and AMIL will work on X-ray sources and AMIL, ICT and NFI on e-beam and SPM platforms for in-line metrology. On the reduction of Total Measurement Uncertainty, Prodrive and AMIL cover the development of an ultra-high precision wafer stage and NVIDIA, AMIL and Prodrive the development of a next generation image processing system. In Mask Infrastructure there are FHG (IISB), ASML, Carl Zeiss covering the creation of a simulation based mask repair strategy and with Carl ZEISS, ASML, PI and UPB HW/SW and process technology for particle removal is created and repair durability is covered with Carl ZEISS, ASML, Suss and UPB. Process technology covers the creation of patterning solutions with the involvement of imec and TEL. On active device selection there will be imec, Cadence, IBS, JSR, Recif and TEL with THERMO enabling advanced TEM characterization. Middle Of Line and Back End Of Line solution development is with imec, TEL, Solmates and Coventor for process modules and Cadence the interface with the design community. On Sustainable Semiconductor Technology and Systems there are imec, Recif and ThermoFisher covering sustainable material and processing alternatives.

The overall objective of the PIn3S project is to realize Pilot Integration of 3nm Semiconductor technology. This covers Process Integration, creation of Lithography Equipment, EUV Mask Repair Equipment and Metrology tools capable to deal with 3D structures, defects analysis, overlay and feature size evaluation. Each of these objectives will be achieved by cooperation between key European equipment developers like; ASML, Zeiss, Thermo Fisher, Applied Materials, Nova, KTI involved with their suppliers, involvement of a strong knowledge network based on Universities of Germany, Heidelberg University Hospital, and the Netherland, TU Delft and the University of Twente, complemented with key Technology Institutes such as imec and Fraunhofer. The project addresses Section 15 “Electronics Components & Systems Process Technology, Equipment, Materials and Manufacturing”, Major Challenge 4 “Maintaining world leadership in Semiconductor Equipment, Materials and Manufacturing solutions” and Major Challenge 1 “Developing advanced logic and memory technology for nanoscale integration and application-driven performance” of the ECSEL JU Annual Work Plan 2018. As set out in the Multi Annual Strategic Plan 2018, PIn3S addresses the ambition for the European Equipment & Manufacturing industry for advanced semiconductor technologies to lead the world in miniaturization by supplying new equipment and materials approximately two years ahead of introduction of volume production of advanced semiconductor manufacturers. With the results of the Pin3S project the consortium builds on realizing IC manufacturers to migrate to the 3nm Technology node which enables a class of new products which have more functionality, more performance and are more power efficient. As such it will form the bases for innovations yet to come enabling solutions that address the societal challenges in communication, mobility, health care, security, energy and safety & security.

In the ID2PPAC project the technology solutions for the 2nm node identified in the preceding project IT2 will be consolidated and integrated with the objective to demonstrate that Performance Power Area and Cost (PPAC) requirements for this generation of leading edge logic technology can be achieved. To continue the Moore’s law trajectory to the 2nm node, while meeting PPAC requirements, the combination of further advancements in EUV lithography & masks, 3D device structures, materials and metrology is required. The strength of the project pivots on the focused engagement of leading expert partners in these key interlocking areas and a shared pilot line. The ID2PPAC project, is expected to enable IC-fabs to do EUV-based, single-print, High Volume Manufacturing for the 2nm node by 2025. This technology evolution is driven by the growing demand for compute power which increases more than exponentially with time and has made the world migrate from 1 billion interconnected devices in the “PC era” to 10 billion in the “Mobile + cloud era” to the future “Intelligence era” in which there will be over 100 billion intelligent connected devices. To enable this growth, the semiconductor industry is continuously pursuing technology innovations to realize this progress as has been predicted by Moore’s Law and will continue to do so. The project will also help to expand Europe's technological capacity to act in this field, which is crucial for digitization, (edge) AI and for solving national, European and global societal challenges and will strengthen the consortium of leading European companies and institutes active in this sector.